6.3 The Memory Hierarchy

The structure of the memory

Recently seen in terms of the relevant cache GPU reading the literature of the time, the time I saw them was at school, when some can not remember, turned down CSAPP review the next cache line, cache set relevant content.

Cache organization

is divided into a number of cache set, each set there are a number of cache line, each valid bit Cache line and contains the tag bits, high to low so that the memory address is divided into three parts:

1. tags, used to determine which cache line set in
2. set index, set to select
3. block offset in cache line, the cache line to memory offset positioning

Three different cache layout

1. direct mapped caches
   1. The simplest, each set only one cache line
   2. The disadvantage is that only when continuous access to different tag multiple memory addresses, can cause continuous cache miss
2. set associative caches
   1. Is a compromise designed two programs
3. full associative caches
   1. The most complex, there is only one set
   2. The disadvantage is that a set has a lot of cache line, find the time complexity of complex tag is high, poor hardware design