After some time ago drew an expansion board Gigabit, Gigabit Ethernet port and Gigabit fiber interface, the two media can be converted by a jumper on the board, the board do when loopback test, found the net mouth will be random dropped frames, while the optical interface is normal, has not found the source of the problem, then doing another project, the need to write MAC timing constraints, find MAC Xilinx hard to provide high 'RX_CLK' timing constraints requirements, the establishment time only 2.5ns, hold time 0.5ns, no matter how repeatedly modify the constraint values do not reach the required constraints, and finally carefully studied it and found PHY chip on the evaluation board, 'RX_CLK' this signal is connected GC_CLK, and my hardware signal design is only connected to the common port IO, when timing constraints, with CLOCK_DEDICETED_ROUTE = FLASE PAR bypass check, so the only access to this dedicated clock pins (or called the global clock pin), the received ordinary IO the mouth, but did not do a good job how common IO port to the introduction of a global clock, on the official forum Xilinx is a foreigner directly pointed out that this just turned into a error warning, does not address the real problem. As a beginner I did not realize, what is the 'real problem', dropped frames happen until after slowly realized FPGA is not so 'simple and easily' I thought before.
Now talk dedicated clock pin, it can be said that the specific reasons occurred due FPGA implementation structure itself, when the FPGA implementation, particularly about the operating clock of the clock supplied from the outside of the FPGA, the clock generated by the PLL or DCM, and FPGA when the FPGA implementation say that, since the design is based on achieving the trigger, which causes, when the layout, but the layout of the same clock domain synchronization device farther apart again the same clock trigger; input data with the clock outputs , there will be a delay, which is reflected in the clock skew (tilt phase), in order to solve this problem, there have been a clock tree, the clock routing in a tree structure, so that the arrival of each of the clock signal with the phase logic unit, so that synchronization can be achieved, which is global clock networks, GC_CLK. That GC_CLK within FPGA is a fixed position, also the corresponding fixed pins, a pin so called global clock pin GC_CLK PIN. In fact, the synthesizer will fan out of the large signal as a global signal and automatically join IBUFG the pin, but only after the pins have a global IBUFG, so if the clock pin in UCF is not used GC_CLKPIN, PAR will error, on the contrary, when a signal distribution is GC_CLK pIN, whether or not a big enough fan, will join IBUFG, this is actually caused by the internal structure of FPGA, only to have IBUFG globally pin, so long as the signal global pins, whether or not the global signal, IBUFG all there.
Let me say the difference between GC_CLK and CC_CLK due GC_CLK PIN is best to use the clock pins, Normally, any clock signal, the hardware connection should be used GC_CLK PIN, but this PIN too little, high-end FPGA will only a dozen, V5 series 200T maximum of only 24, so often can not meet the actual needs of the clock, then appeared substitute CC_CLK, CC_CLK can only guarantee the same or adjacent BANK BANK clock signal in phase, and can not drive with BUFER, (which I do not quite understand the future uses will add up.) simply put, is to have GC_CLK will use GC_CLK, did not, to use CC_CLK, if ordinary IO port, there will be some issues to note.
Before returning to the clock pin of said operation clock in the FPGA is fixed, nothing to say, some of the most global clock pin, a clock internally generated by DCM or PLL, Output DCM will automatically access the global clock network, in fact, is the last one I had ignored before, with the line clock input and output, if received on a normal IO on the hardware, which is a little tragedy, although you can use to tap into BUFG global clock networks, however, from PAD to BUFG output has the inherent delay of 10ns. This 10ns can not be eliminated, so if the clock frequency is more than about 20M, skew will be relatively large. Some approaches: cascading two phase modulation DCM BUFG + DCM + DCM. Gigabit Ethernet ports to run 125Mbps, the clock cycle is 8ns, if the inherent delay is 10ns, then there is a delay of 1/4 cycle, I intend to phase modulation with a 90 ° before, after a 180 ° phase modulation, so that you can achieve the same phase of the bar. But the ensuing question is whether the inherent delay of 10ns is stable (the amount of delay is the official forum of a Daniel said, did not find a reliable source), whether or phasing to ensure that no two DCM deviation. This is the actual procedure depends on the result of the board to run to conclusions.
After the board back, in practice, there have been the following phenomenon: a fixed minimum frame interval send Ethernet frames to Gigabit standard 96ns, wrong frame phenomenon occurs, if Shizhao standard 9600ns, there would be no dropped frames I think the interface board is not perfectly meet the requirements of high-speed communication, the reason is most likely to use the dedicated pin or pins through the interface board can not support high-speed transmission, only eleven again ruled out.
