LCD data sheet resolve

Table of Contents

First, the basic information (resolution size)

Second, the timing resolve

2.1, the level of horizontal

2.2, vertical vertical

2.3, polarity clock phase (rising or falling edge)

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First, the basic information (resolution size)

Second, the timing resolve

linux-driven development of the principle of LCD timing analysis (two)

2.1, the level of horizontal

 

HS Blanking = HSPW + HBPD = 46
where HSPW can be set to 10, then 36 is HbpD.
hsync_len (HSPW): 10
right_margin (HFPD): 210
left_margin (HbpD): 36 

2.2, vertical  vertical

VS Blanking = VSPW + VBPD = 23
where VSPW can be set to 8, 15 is the VBPD.
vsync_len (VSPW):. 8
lower_margin (VFPD): 22 is
up_margin (HbpD): 15
 

2.3, polarity clock phase (rising or falling edge)

 

 

1.IHSYNC, IVSYNC, VDEN to EXYNOS4412 timing as a reference point controller is normal, if the polarity of the same, configured as Normal , otherwise Inverted .