This switched: own micro-channel public number "IC design and EDA tutorial"
Tweets main elements:
- LPP: Low Power Placement
- GLPO: Gate-level power opt
Low-power technology:
- Buffer Insertion
- Cell Sizing
- Pin Swapping
- Phase Assignment
- Technology Mapping
- Factoring
What strategies can be applied to low-power chip physical layout stage to reduce power consumption of the chip it?
Perform some setup static power optimization:
set_scenario_options -leakage_power true: 1. For MCMM design, we also need to specify which scenario when creating the scenario can be used to optimize the static power consumption, generally select those static power consumption is very large scenario, the command is
2. Specify multiple threshold voltages constraint command: set_multi_vth_constraint
Performing dynamic power optimization process: performing LPP dynamic power reduction process is as follows:
set_scenario_options -dynamic_power true: 1. For MCMM design, we first need to specify which scenario can be used to optimize the dynamic power at the time of creation scenario, the command is
2. Prior layout netlist file read saif dynamic simulation obtained, which records the Net and Cell Swithing Activity. The command is: read_saif. After which the LPP ICC can function, so that some of Cell ICC will automatically move in the layout stage, shortening the length of the high Net inverted, reduce the capacitance on the Net, connected thereto Cell reducing dynamic power consumption. If you do not saif file, need and let the future pass before the layout of the input port Toggle Rate design, if you know some intermediate nodes Toggle Rate can also be set so that power analysis will be more accurate.
This option is off by default, need to open before the layout.
ICC is an older version of the following ways open: set_power_options -low_power_placement true
Flow is as follows:
Note: In the new version of the ICC, set_power_options command has been abolished; if it is a new version of the software can use the following command: set_optimize_pre_cts_power_options -low_power_placement true
GLPO perform dynamic power reduction process is as follows: When we can optimize the layout (Gate-level power optimization, GLPO ) to reduce power consumption optimization logic level power through the door.
Gate-level power optimization techniques:
1. Buffer Insertion: Insert Buffer to reduce the load capacitance, and reduce input Transition time, thereby reducing the dynamic power consumption.
2. Cell Sizing: reduce the capacitance High Switching Activity on the network, to shorten the time to lower the Transition Inernal Power.
3. The switching pin (Pin Swapping): a high flip Net pin is connected to the low capacitance of the Cell.
4. The phase assignment (Phase Assignment): phase inversion to remove high-inverting inverter
The mapping process (Technology Mapping): High Hide inverted AND gate network 4 such as the input of the Cell, AND4 + INV we can use the program to achieve, but also through NAND2 + NOR2 program implemented in two schemes Area and Delay Comparative Energy aspects as follows:
PPA comparison:
Area: Scheme (a) is more compact, and therefore a smaller area;
Speed: two-stage structure are two programs, program (a) than (b) faster, or at least as fast;
Energy: Scheme (a) a high internal network is hidden inverted, thus consuming less energy, and the effect is obvious .
6. 代数变换分解（Algebraic Transformations Factoring）：修改网络结构，降低电容，但可能会增加活动性。
注意：可以在place_opt期间同时执行GLPO，LPP和泄漏功耗优化，也可以在place_opt之后，在psynopt期间单独执行GLPO，可以获得类似的结果，并可能会降低整体运行时间。
旧版ICC整体Flow如下：
在新版ICC里面，set_power_options命令被废除，同样通过set_scenario_options -dynamic_power true选取进行动态功耗优化的scenario，之后用place_opt -power来进行GLPO。
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