DC provides a file, .synopsys_dc.setup.
In this file you can edit the project needed technology library, symbol library, and have a good script file definitions.
Wherein the technology library, symbol library Yes. db file format.
General .synopsys_dc.setup file will have three:
a real synopsys under the installation directory, a user in the directory, these two are not the best move, one in the current working directory, which is where you start the catalog DC, no you need to create your own (usually hidden away, enter vi synopsys_dc.setup directly in the console lab2 directory).
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Library Setup（库设置）
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
set search_path ""
set target_library ""##目标库
set link_library ""##连接库
set symbol_library ""##符号库 除此之外还有 synthetic library 综合库
## link library和target library 统称为 technology library 即工艺库，综合库，由半导体制造商提供，包含相关的cell的信息及约束标准，
## target library ：DC用于创建实际电路的库，再门级优化及映射的时候提供生成网表的cell，
##link library：提供设计网表中的cell，可以跟目标库使用同一个库，但是DC并不会用link library中的库来综合设计。当读入设计时，DC会读入link library变量指定的库，但当连接设计时，DC会先搜集其内存中已有的库，然后在搜集由link library指定的库，
##注：如果读入的设计是门级网表时，需要把link library指向生成该门级网表的库文件。
##symbol library：是指DC GUI模式下展示的cell的图形符号，如果使用tcl模式是无需指定符号库的。
##synthetic library 即为designware library ，虽然名字上为综合库，但是常被称为IP库
############ Do NOT edit below this line ############
#####################################################
echo "\n\nSettings:"
echo "search_path: $search_path"
echo "link_library: $link_library"
echo "target_library: $target_library"
echo "symbol_library: $symbol_library"
define_design_lib DEFAULT -path ./analyzed
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# History
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
history keep 200
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Aliases
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
alias h history
alias rc "report_constraint -all_violators"
alias rt report_timing
alias ra report_area
alias ra report_area
alias page_on {set sh_enable_page_mode true}
alias page_off {set sh_enable_page_mode false}
alias fr "remove_design -designs"
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# Alib for compile_ultra
# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
# set alib_library_analysis_path [get_unix_variable HOME]
set alib_library_analysis_path ..
echo "\n\nI am ready...\n"
Contents of the entire setup file in the case has not been set on this line 49
file structure in the Lab:
Mapped: store the file directory after the comprehensive completion;
Unmapped: storage integrated time without the file directory technology library mapping
Script: storage constraint script file ;
Rtl: storage verilog model.
DC will bring up the UI interface, you will see in the log area settings related information, here's four libraries are empty. Unset
when you've set up will have
