DC integrated whole process (Global View)
1. Prepare the technology library, HDL code and constraints files.
2. Start the configuration environment, mainly the configuration of the three libraries, target link symbel library.
3. Read the design, is designed to convert the file format into an intermediate DC, i.e. GTECH format, designed to read in two ways: GUI is also read in tcl analyze & elaborate, both of which are substantially equivalent just read some more readable file format, such as. db library file.
4. Define the design environment: include process parameters (temperature, voltage, etc.), I / O port attributes, wire_load statistical model.
5. Set design constraints: Constraints include design rules and optimization constraints, design rule constraints are specified by the process library, it must be designed to ensure that the circuit works properly bound; optimization constraints: is specified by the user, timing, area optimization goals.
6. Select Compile policy: mainly top-down bottom-up, ( about this two strategy in a top down strategy, the top-level design and design sub-compiled together, and all the environmental constraints set for top-level design, although such policies are automatically considered related to interior design, but this strategy is not suitable for large-scale and design, as compiled top down strategy, so the design must be in memory and hardware resources consumed large. in the bottom up strategy, designed to separate the child restraint when the child successfully design after compilation, is set to dont_touch properties that prevent the compilation process is modified after, all with sub-layer design after compilation, on the re-design compiler father, until top-level design is compiled .Bottom up policy allows large-scale design, because the policy does not require all the memory-resident design at the same time.)
7. compilation, synthesis and optimization of process execution compile command.
8. analyze and solve design problems in a comprehensive report by DC, analyze and solve design problems in order to improve the overall results
9. The storage design data, the design does not automatically result of DC integrated storage, storing the design data manually when leaving DC. Such as storage netlist, delay information.
