Second lesson
Data Technology and Design
1. Loading RTL design and logical bank (i.e., Verilog files and file db)
2. Loading physical technology and design data
including milkway derectories, tf file, rc modeling files, floorplan data.
Need to be familiar with some of the protocols and ports, such as PCIE protocol, AMPA agreement (?), AMBA bus protocol, DMA, CPU and so on.
Even more than the back-end design and verification staff personnel to be more understanding.
- This lesson needs to master command
Settings file
- .synopsys_dc.setup
set_app_var target_library your_library.db
set_app_var link_library {* your_library.db}
set_app_var symbol_library your_library.sdb
set_app_var search_path " .<Install_dir>/libraries/syn ..."
DC Once started, the three directory name with this file will be executed sequentially, are:
- $SYNOPSYS/admin/setup(default)
- ~user (user’s general)
- DC startup directory (CWD)
The first priority of the lowest, the third highest priority, modify settings when you need to modify only the third is the start directory of files, ensure the integrity of the first two documents .
- Library target
target Library pointing manufacturers to process library, based on the process used to create a library of gate-level netlist during compilation
printvar target_library //打印参数
set_app_var target_library libs/65n_wc.db //设置目标库
set target_library libs/65n_wc.db //set_app_var更容易发现错误，比set更安全
write -format berilog -output mapped/MYREG_mapped.v //以verilog形式保存生成的netlist
Be sure to set the target library before compile command, otherwise there is no meaning
to generate use netlist: Used after imitation, in addition to the specified file will generate .sdf and verilog .ddc (.sdc) file generated netlist
.ddc ≈ .v + .sdc, but the content .ddc file contains both actually add up to more than
- link_library
Link Library and target library sometimes refer to the same thing, but in fact there are some differences.
For example, some companies only provide the provision of IP .db / .ddc file that can be instantiated in code to use but can not view this file you need to link library contains among DC for integrated use.
DC Looking order of the modules (1) find and design of the same name of the module (2) in the DC software's memory to link_library specified list of library looking for the same library_cell name Module
(asterisk * denotes first in DC's memory of them search for)
set_app_var link_library "* $target_library"
- search_path
also can use search_path command to tell DC need to go look for verilog file, so that the front of the .v file path can be omitted.
read_verilog MYREG_mapped.v //只要已经在search_path中指定之前的路径，就不需要在命令中打出来
search_path = " .<Install_dir>/libraries/syn" //这里的小数点代表__启动DC__的目录
The search path (1) cwd i.e. start the software catalog (2) search_path listed in the directory
RTL level code read
- read_verilog
using current_design hierarchy is currently located is determined (Hierarchy) after reading the .v file read_verilog
check_design can help check code again, for example, (1) there is also connected to the input port is not or does (2) the presence of repeated or recursive structure of the embodiment of ; returns 0 if the code indicates that there are problems, returns 1 shows that can be integrated.
//向DC载入RTL级代码的过程
dc_shell-topo> read_verilog {A.v B.v TOP.v}
dc_shell-topo> current_design MY_TOP
dc_shell-topo> link
dc_shell-topo> check_design
dc_shell-topo> source TOP.con
- analyze & elaborate
plus with analyze & elaborate way, this method does not require current_design or link command
-format vhdl and SV also supports, but not all languages can be integrated SV
dc_shell-topo> analyze -format verilog {A.v TOP.v}
dc_shell-topo> elaborate MY_TOP
analyze command will read the documents into .pvl file, elborate command and then GTECH file format that .pvl
elaborate command can specify not only the top level, specify parameter values -parameters option to override the default parameter values in the module.
dc_shell-topo> elaborate MY_TOP -parameters "A_WIDTH=9, B_WIDTH=16"
- Save ddc file
before compiling the link (elaborate), held by GTECH timely written ddc file to avoid wasting time secondary operations, but we must remember that once the source file is modified, .ddc file also re-integrated generation
dc_shell> write -format ddc -hier -output unmpad/MY_TOP.ddc
Integrated DC is based on the path completed, the circuit diagram of each path must have the appropriate constraints.
Note: This compilation of non-vcs for verilog compile files.
After compiling is completed also need to save files for backend ddc, the following sequence of commands:
dc_shell> link
dc_shell> check_design
dc_shell> write -format ddc -hier -output unmapd/MY_TOP.ddc
dc_shell> source TOP.con
dc_shell> check_timing
dc_shell> compile_ultra
dc_shell> change_names -rule verilog -hier
dc_shell> write -format verilog -hier -output mapd/MY_TOP._net.v //提供给非synopsys的后端软件使用
dc_shell> write -format ddc -hier -outpu mapd/MY_TOP.ddc //提供给支持synopsys格式的后端软件使用
Examples
read_verilog -rtl [list top.v fsm_moore.v counter.v]
Here [list] represents, each object after the foregoing list are handed commands and options to complete, the command corresponding to the same compressed together.
list_libs
This command lists the names of all libraries, and the corresponding file path.
report_lib [库的名字]
Then the above command to display the details specified library.
If you can not remember a command usefulness can use the following options
[命令] -help
man [命令]
After the DC code files can be loaded with list_designs display all the files have been read into the design, the back with an asterisk (*) indicates that this is a design file the user is currently located.
Note: Only the sub-module top layer and top layer will be included in a comprehensive, integrated and therefore before to determine their location.
