first lesson
- Importing
Target: a generally need to understand how their configuration code written after conversion circuits
DC features: mapping a circuit diagram of the base unit RTL level code provided by the described process according to the gate-level netlist library vendors
DC operation requires three conditions:
1.RTL code
2. Process library
3. Constraints File
Comprehensive general DC is not the time to consider the layout information. If you need to consider the layout parameters can be extracted from the back-end, integrated as a physical constraint.
Code must go through in order to ensure complete functional verification of integrated circuit out to be correct.
- DC Integrated Process
All languages internal DC will be converted into GTECH
GTECH library is Synopsys provided by universal, independent process libraries. Synopsys synthesis tools provided by DC to comprehensive divided into three steps: synthesis = translation + mapping + optimization . Translation refers to the design of the HDL description into GTECH library of logic elements; refers to the Mapping Mapping GTECH library element to a particular semiconductor process library that may contain a circuit netlist relevant process parameters. Optimization is based on the delay set designer, the area, the line load models integrated circuit netlist constraints imposed on further optimization of the process.
DC earlier documents produced to .db suffix, now .ddc suffix, .ddc file contains timing information, delay information, constraint information, very comprehensive.
- Delay calculation
Circuit delay = delay + line delay device
There are two delay lines is calculated by:
1. Load mode line (WLM), in model-based RC circuit technology library sizes provide different interconnect model (model successfully extracted from the sheet having passed the chip).
2. topology mode (Topographical), to use the DC, the rear end of the circuit is derived prelayout about what structure, then back to the software arrangement, the configuration of the delay line is calculated. more accurate
Three ways to open the topology model:
Other commands:
- Examples
在工艺库中一般会有文件名相同的.db和.lib文件，.db文件专门用于DC软件，.lib软件用于供人阅读。
.lib软件可以用library compiler转化为.db文件，dc文件同时支持.ddc文件和.db文件。
dc_shell -topo | tee dc_start.log符号“|”表示管道命令，将符号前面的命令交给后面的操作去完成，在这里是将命令交给tee去记录综合的过程并生成log文件dc_start.log。
在dc_shell里面使用linux命令需要先输入sh。
若不设置工艺库，则在DC中综合出的是JTAG电路图，也就是由DC公司直接提供的库综合出来的
