x86 architecture --PCI IRQ

Brief

In the x86 architecture --8259A interrupt controller , we have to introduce, through 8259A interrupt controller, the system can connect up to 64 interrupt sources, but in actual use, if you really use the 8259A 8 pieces, the system design It will be very difficult. Therefore, in actual use, we can use a general or a 8259A chip 2, thus constituting a maximum of 16 interrupt (one or cascaded with, the actual on 15).

However, with the development of computer systems, need access to more and more equipment, especially the introduction of PCI devices, resulting in the number of interruptions it is not enough, in order to solve this problem, we introduced the concept of interrupt sharing, in order to better support PCI devices, and the introduction of PCI interrupt (ie article title referred PCI IRQ).

This paper describes the PCI IRQ. Note that, this thing PCI devices need extra pins to support, follow-up with the introduction of MSI interrupts, PCI IRQ has basically been eliminated, so this is also part of the archaeological culture.

 

Description PCI specification IRQ

Below is specified the device PIN pin PCI specification:

Note that the red box part of PIN feet, they are for the interruption, they have the following characteristics:

1. Alternatively, as in the case of MSI, the interrupt walk PCI protocol, no additional pins to support;

2. A total of four pins, dB is ABCD;

3. For multi-function (Multi-Functions) devices will be used to pin outside the INTA #, otherwise you can only use INTA #;

These are hardware configuration, when the pin is determined, the need to configure the software, which requires use of the contents inside the PCI configuration space, as follows:

This is the PCI configuration space, the red part is configured on the PCI IRQ.

Interrupt Pin: Specifies the INTA # / INTB # / INTC # / INTD # one, 1 INTA #, 2 denotes INTB #, and so on;

Interrupt Line: Specifies the PCI IRQ interrupt controller is connected to which of the interrupt (interrupt number, such as 8259A, it is interesting that the general 8259A interrupt A / B is the flow out to a PCI IRQ, a correspondence relationship just formed, However, this correspondence is not required).

 

Stop routing

PCI规范中的规定比较简单,已经在上面说明。

但是需要注意的是,PCI设备不是直接连接在中断控制器上的,而连接在芯片组(以x86为例)上的。

因此当中断发生之后,是先到芯片组,然后再通过芯片组到中断控制器的,中间需要芯片组的处理,我们将之称为中断路由。

如图所示:

这里的可编程中断路由器就在芯片组中(实际上8259A通常也在芯片组中)。

通过对芯片组的配置,才能将中断对应到8259A上的特定中断上。

至于如何配置这个路由关系,需要根据不同的芯片组来实际设定,可以参考对应芯片组的DataSheet,这里不做说明。

 

关于中断的处理

这是一个遗留问题。

我们知道系统都不同的中断都会有处理函数,因此对PCI中断也有处理函数。

但是中断时共享的,假设不同设备的INTA#都对应同一个处理函数,那么系统程序该如何来做区分呢?

目前对于这个问题还不是很了解,待研究。

关于这一点,可以参考PCI 中断路由机制中第三节的说明,比较有道理。

 

发布了197 篇原创文章 · 获赞 193 · 访问量 60万+

Guess you like

Origin blog.csdn.net/jiangwei0512/article/details/102255112