Write at the top:
In view of the current technical level of the blogger, I divide the current CPU processor architecture into two types
Please check the first chapter of the planning group overview:
https://blog.csdn.net/Vast_Wang/article/details/108893893
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The origin of X86:
Both the CPU and memory transfer data by bus.
In fact, there are mainly two types of data on the bus. One is address data , that is, where I want to get the data in the memory. This type of bus is called an address bus ;
The other type is real data, and this type of bus is called Data Bus .
So, the bus is actually a bit like a highway connecting the two devices of CPU and memory. The number of bits in the bus is like saying that the highway has several lanes.
But the meaning of the number of bits of these two buses is different.
The number of bits in the address bus determines how wide the address range can be accessed.
For example, if there are only two positions, the CPU can only recognize the four positions 00, 01, 10, and 11, and if there are more than four positions, it cannot be distinguished. The more bits, the more locations can be accessed, and the wider the range of memory that can be managed.
The number of bits of the data bus determines how many data can be brought in at a time. For example, if there are only two digits, the CPU can only take two digits from the memory at a time. If you want to take eight, you have to take it four times. The more digits, the more data you can get at one time, and the faster the access speed
x86 has become an important part of the history of open platforms
Is there a standard for the number of bits of the bus in the CPU? If there is no standard, then the operating system is very difficult to handle as software, because the software layer cannot implement general arithmetic logic. This is like many non-standard components, you burn your circuit board, I burn my circuit board, no one can use each other.
In the early days, IBM relied on mainframe technology to become the leader of the computer market, until the rise of personal computers and the birth of Apple. However, at that time, whether it was a mainframe or a personal computer, each CPU architecture was different . If this has always been the case, personal computers, tablets, mobile phones, etc., cannot form a unified system, and there will be no general-purpose computers we are now, let alone cloud computing, big data, and other unified large platforms.
Fortunately, history has pushed the x86 platform to an open, unified, and compatible position. We continue to look at the story of IBM and x86. When IBM started working on the IBM PC, it didn't let the best Watson Lab do research and development , but handed it over to another team.
In one year, it was impossible to complete all the software and hardware by self-research, so they used Intel's 8088 chip as the CPU and Microsoft's MS-DOS as the operating system.
Who would have thought that IBM PCs sold super well, so good that they were sued for monopolizing the market .
When IBM was forced to disclose some technologies, the subsequent emergence of countless IBM-PC compatible companies led to the emergence of Hewlett-Packard, Compaq, Dell, etc. that later occupied the market.
Being able to open up one's own technology is an amazing thing. From the perspective of technology and development, it will make a technology spread out on a large scale and form an industry standard. For example, the commonly used Android phones nowadays, without an open Android system, we would not be able to enjoy so many different types of phones.
The same was true for PCs of the year. Intel's technology has therefore become the industry's open de facto standard. Since this series started in 8086, it is called x86 architecture.
Later, Intel's CPU data bus and address bus became wider and wider, and the processing power became stronger.
But we can't forget three points, one is standard, the other is openness, and the third is compatibility. Because if you want such a large software and hardware ecosystem to be based on this architecture and meet its standards, if it is closed or incompatible, no one will agree.
The bus bit number of the first 8086 architecture is 16
The 80386 was 32-bit since the beginning, and it lasted a long time. Until the advent of 64-bit
The 64-bit machine is called x64, in fact it is called x86-64!!! It also belongs to the x86 architecture
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Speaking from the principle of 8086
After talking about the history of x86, let's look at the most classic processor in x86, the 8086 processor.
Although it is very old, many of the features in our current operating system are related to it and have always been compatible. Let's look at the components inside the CPU after zooming in. You can see this picture I drew.
Let's look at the data unit first.
In order to temporarily store data, there are 8 16-bit general-purpose registers inside the 8086 processor, which are the data units inside the CPU just mentioned, which are AX, BX, CX, DX, SP, BP, SI, DI.
These registers are mainly used to temporarily store data during calculations. These registers are more flexible. Among them, AX, BX, CX, and DX can be divided into two 8-bit registers for use, namely AH, AL, BH, BL, CH, CL, DH, DL, where H is High. L means Low (low bit).
In this way, relatively long data can be temporarily stored, and relatively short data can also be temporarily stored. You might say that 16 bits are not long, but don’t forget, that was when computers were just starting out.
Then we look at the control unit.
The IP register is the Instruction Pointer Register, which points to the location of the next instruction in the code segment.
The CPU will continuously load instructions from the code segment of the memory to the instruction queue of the CPU based on it, and then hand them over to the arithmetic unit for execution.
What if you need to switch processes? Each process is divided into code segment and data segment. In order to point to the address space of different processes, there are four 16-bit segment registers, namely CS, DS, SS, ES.
Among them, CS is the Code Segment Register, through which you can find the location of the code in the memory;
DS is the register of the data segment, through which you can find the location of the data in the memory.
SS is the Stack Register.
The stack is a special data structure in the running of the program. Data access can only be done from one end. Adhering to the principle of last in first out, push means pushing into the stack, and pop means popping.
The starting address of a segment is stored in both CS and DS.
The offset of the code segment is in the IP register, and the offset of the data segment is in the general-purpose register.
The problem comes at this time. Both CS and DS are 16-bit, that is to say, the start address is both 16-bit, the IP register and general register are both 16-bit, and the offset is also 16-bit, but the 8086 is The address bus address is 20 bits.
How to make up these 20 people? The method is "starting address*16+offset", that is, the value in CS and DS is shifted 4 bits to the left to become 20 bits, plus 16 bits of offset, so that you can get the final 20 bits The data address.
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2^4=16, starting address * 16 is equivalent to left shifting 4 bits =
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From this calculation method, it can be calculated that no matter how large the real memory is, for the 8086 with only a 20-bit address bus, the distinguishable address is only 2^20=1M, and it cannot be accessed beyond this space.
Why is this again? If you want to visit the place of 1M+X, this position has exceeded 20 bits. Since the address bus has only 20 bits , the part of the bus with more than 20 bits cannot be sent out at all, so X is still sent out, and finally it will Visit the position of X within 1M.
What is the maximum size of that segment? Because the offset can only be 16 bits, the maximum size of a segment is 2^16=64k
Isn't it pitiful? For the 8086CPU, only 1M of memory space can be accessed at most, and it must be divided into multiple segments, each with a maximum of 64K. Although we now seem to be unimaginably small and useless at all, it was actually enough at the time.
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Let’s talk about 32-bit processors
Of course, with the rapid development of computers, the memory became larger and the bus became wider.
In a 32-bit processor, there are 32 address buses, which can access 2^32=4G of memory.
Using the original model will definitely not work, but the original model cannot be completely abandoned because the architecture is open.
"Open" means that a large number of other companies' software and hardware are implemented based on this architecture. You can't do whatever you want. You must be compatible with the original architecture and always be compatible, so that everyone is willing to follow you. The open platform has been playing. If you change things day and night, other manufacturers will be miserable. If it is a closed architecture, there is no problem. The hardware, operating system, and even the software above are all made by yourself, and you can change it as you want.
Let's talk about how to maintain compatibility based on an open architecture?
First of all, general-purpose registers have extensions , which can extend 8 16-bits to 8 32-bits, but still retain 16-bit and 8-bit usage.
Among them, the instruction pointer register IP that points to the next instruction will be expanded to 32 bits, which is also compatible with 16 bits.
As shown below:
And the change is relatively large, a bit incompatible is the segment register (Segment Register).
Because the original model is actually a bit nondescript, because it does not regard 16 bits as the starting address of a segment, nor does it expand to 8 bits or 16 bits. Instead, according to the hardware at the time, it makes a 20-bit which is not good enough. the address of.
In this way, it must be shifted four bits to the left each time, which means that the starting address of the segment cannot be any place, but a place that can divide 16 evenly.
If the new segment registers are changed to 32-bit, it is obvious that all the 4G memory can be accessed, and can't shift left by four bits?
Let us simply redefine it.
CS, SS, DS, ES are still 16 bits, but they are no longer the starting address of the segment. The starting address of the segment is placed somewhere in memory.
This place is a table, and one item in the table is a segment descriptor (Segment Descriptor).
This is the starting address of the real segment. Which item in this table is stored in the segment register is called the selector.
In this way, a segment start address obtained directly from the segment register becomes an item in the table found indirectly from the segment register, and then the segment start address is obtained from an item in the table. This section start address will be very flexible.
Of course, in order to quickly get the start address of the segment, the segment register will be taken from the memory to the descriptor cache of the CPU.
When the previous model appeared, I didn't expect to become a standard, so the design was not so flexible.
Therefore, under the 32-bit system architecture, we call the former mode the Real Pattern, and the latter mode the Protected Pattern.
When the system is just started, the CPU is in real mode, and it is compatible with the original mode at this time.
In other words, even if you buy a 32-bit CPU, it still supports running in the original mode, but it's just a bit faster.
When you need more memory, you can follow certain rules, perform a series of operations, and then switch to protected mode, you can use the more powerful capabilities of the 32-bit CPU.
This means that it cannot be seamlessly compatible, but compatibility by switching modes is acceptable. In the next few sections, we will take a look at how the CPU gradually changes from real mode to protected mode from startup.
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