This is a summary of the main topics of the classic, if want to see a summary of knowledge, and I can see another blog: microelectronic circuits - Closing summary
I. Introduction
1, the first year of the invention of the transistor? : 1947
2, the inventor at the time worked for which company? : Bell Lab
3, the first integrated circuit Year invention? : 1958
4, the inventor at the time worked for which company? : TI
5, the first computer was born the year? : 1946
6, the inventor at the time worked for which company? : Bell Lab
7, the first year mos tube birth? : 1960
8, CMOS tube birth year? : 1963
Second, the basic element
1, consider the standard 0.13μm CMOS process NMOS transistor, when the threshold voltage of zero bias lining VT = 0.3V, the gate oxide thickness tox = 260nm, the substrate doping concentration NA = 2 × 1017cm-3, the substrate is grounded. If the time source VS = 0.3V, NMOS threshold voltage variation tube at room number?
This question is mainly on the threshold voltage of the formula:
focus we need to calculate the body effect coefficient according to his out value
ε which is a constant, q is constant, while the Na has been given of the title, we need to calculate only deleted oxide layer capacitor, according to the formula:
can be calculated on the heald body effect coefficient, and the Fermi level must have two [Phi], the Fermi level of the formula:
wherein the KT / q is the thermal voltage at ordinary temperature, Ni is present carrier concentration of the card, it is to be constant, can be substituted into the calculation. Since the source voltage VS = 0.3, then the bottom voltage source = -0.3, into the initial agreement, we can calculate the final threshold voltage
This question is difficult, but you know, at the time of the examination, all the formulas, constants the teacher will give out, the focus is on how we use (~ want it).
2, considering the standard 0.13μm CMOS technology NMOS transistor width to length ratio W / L = 0.26μm / 0.13μm, gate oxide thickness tox = 26Å, the electron mobility μn = 220cm2 / V · s at room temperature, the threshold voltage VT = 0.3V, calculated VGS = 1.0V, VDS = 0.2V and 1.0V ID when the size.
This question we have to calculate the size of the drain-source current, according to the first given VGS and VT can know VGS> VT, whereas when the time VDS = 0.2, VDS <VGS-VT, this time in the linear region described, using formula:
Accordingly, the time when VDS = 1, VDS> VDS-VT, described in the saturation region at this time, using the formula:
in this case we have only to be calculated this constant beta], into the formula:
Similarly, W and L have given, μn also been given only Ctox puncturing oxide capacitance needs to be calculated, into the formula:
At this point, all the parameters have been calculated is completed, you can get the value of the leakage current.
You can see, the standard 0.13μm often nmos tube, we can remember what the value of his or ε Ctox value of the capacitance of the oxide layer is deleted, it is 3.9 8.85 10 -14 / tox, and tox unit A 10 -8
3, the N-type semiconductor, for example, his majority carriers are free electrons, i.e., the free electron concentration n> hole concentration p, whether he maintain electroneutrality? why?
It is to keep the electrically neutral.
From a micro perspective, no matter how the child is still low birth rate, it is outside the terms of the atomic nucleus. Take the title Case N-type semiconductor. Since the N-type semiconductor doped with Group 5 is made, resulting in the presence of free electrons in the crystal lattice more constituting the majority carriers.
From the macroscopic point of view, the intrinsic semiconductor is electrically neutral, the doping is electrically neutral, so the number of all electronic ** (whether or not the free electrons) ** and the number of protons in the nucleus are equal, so that no significant outside electrical.
4, in semiconductors, which are positively charged? : Ionized donor, hole
5, in semiconductors, which are negatively charged? : Ionized acceptor, free electron
6, for a semiconductor in terms have the following formula:
For a donor impurity, may be considered as the number of electrons holes where d = d + ions donor . Wherein Note that, where the number of electrons is not equal to n, but only electrons generated from donor impurities.
For an acceptor impurity, it can be considered as the number of holes a + a = number of electrons acceptor ions . Wherein Note that, where the number of holes is not equal to p, but only by the hole produced by impurities.
7, each of the MOS transistors of FIG what type, the gate of each MOS transistor indicated, a source, a drain, analyze their operating state, provided the threshold voltage of the absolute value of all the transistors are 1V.
(a) Enhanced NMOS, the gate is left, upper drain electrode, the source electrode, VT = 1V, VG-VT > VDS. Operating in the linear region of
enhanced nmos (b), a source left, upper gate, the drain, VT = 1V, VDS> VG -VT. Operates in a saturation region
© NMOS depletion type, a gate is left, upper drain electrode, the source electrode, VT = -1V, VDS> VG -VT. Operates in a saturation region
(D) Enhanced PMOS, the gate of the left, upper source electrode, the drain, VT = -1V, VDS> VG -VT. Work in the linear region
8、如图所示，M1 和 M2 两管串联，且 VB < VG-VT < VA，请问：
（1） 若都是 NMOS，它们各工作再什么状态？
（2） 若都是 PMOS，它们各工作在什么状态？
（3） 证明两管串联的等效导电因子是 Keff = K1K2/(K1 +K2)。
解：
（1）假定VC的值，根据VB<VG-VT<VA，可以得到两种情况：
①M1饱和且M2线性（VC<VG-VT）
②M1截止且M2饱和（VC>VG-VT）
假设M1截止、M2饱和，则上nmos电流为0，下nmos电流大于0，VC被下拉，电路处于非稳态，所以VC会继续下降到VC<VG-VT，使M1导通，M2线性，最终达到M1饱和，M2线性的状态，此时为稳态。
（2）同上，得出M1线性、M2饱和
（3）假设都是nmos管，由于VB<VG-VT<VA得到：
ID1=K1(VG-VT-VC)^2
ID2=K2[(VG-VT-VB)2-(VG-VT-VC)2]
IDeff=Keff(VG-VT-VB)^2
由此可以得到：
又因为ID1=ID2=IDeff
化简后可得Keff=K1K2/(K1 +K2)
三、反相器
1、对于W/L=20/1的晶体管，其 KP和KN分别是多少？
我们可以根据K值的公式：
题目中给出的K‘实际上就是除去了宽长比的K值，即K‘=1/2μCox
所以，这道题已经很简单了，直接代入公式就可以。
2、CMOS反相器中(W/L)P=(W/L)N时，KR为多少？ 计算这个KR值时，CMOS反相器由逻辑阈值点确定的最大噪声容限为多少？（VDD=2.5V, VTN=0.6V, VTP=-0.6V）
这道题我们需要计算Kr=KN/KP，直接带入公式可以求出大概为2.5
要计算最大噪声容限，我们需要计算出转换电平Vit的值，即公式：
此时我们已经有所有的值，那么直接算出转换电平的值，而最大噪声容限是VDD-Vit与Vit之间的小值，可以计算出
3、求图中反相器的最大电流？
想要计算最大电流说明是双饱和区的时候，即公式：
由于K‘都已经给出，且VT都给出了，宽长比在图中给出分别是5/1和2/1，VDD为2.5V，那么就可以直接计算出此时的Vin，然后带入等式两边任意一个就可以计算出此时的漏电流大小。
4、计算图中反相器平均传输延迟tP，其中CL=1pF
想要计算平均延迟时间，我们需要用到公式：
题目中已经给出了负载电容的值，高电平为2.5V，K值可计算，VT已经给出，直接带公式就可以。
四、基本单元电路
1、用静态 CMOS 电路:
(a) 实现两输入或非门
解：这道题可以看出，我们假设输入是A和B，输出为Y，此时nmos下拉电路负责A+B，pmos上拉电路负责!A·!B，或者可以通过真值表得到相同的结果，我们最终知道，或非的话，pmos是串联的，nmos是并联的
(b) 如果电路中各管的导电因子相同，即 KN=KP, VTN=-VTP，求输入 A 和 B 同步变化下的 KN,eff, KP,eff, Vit；求输入 A=0V,B 变化下的 KN,eff, KP,eff, Vit
解：这道题实际上就是让我们求等效的但cmos电路，我们需要知道串联和并联时候的电流关系，一nmos模块为例，并联的时候，可有如下的电流关系
所以可以有
同理，对pmos上拉电路，由于是串联的，同样有
即
综上，我们带入求Vit的公式，就可以有如下的结果：
当A和B都是高电平的时候
当A是低电平，B变化的情况下，上述电路中MN1截止，只有MN2起作用，而MP1\MP2都起作用，此时有
带入有
© 根据(b)的结果参考教材图 4.1-9 试定性的画出两输入或非门直流电压传输特性
解：根据第二问的结果我们知道，我们需要画出两条线，分别针对两种情况，故此可以有：
2、 画出利用静态电路实现
的电路图，要求使用的 MOS 管最少；假定
, The NMOS carrier mobility was 2.5 times the PMOS transistor, and design of each tube width to length ratio such that the circuit rise and fall in the worst case of equal time. (Assuming the minimum process NMOS W / L of 2/1)
solution: First, we want to be treated on the type, this time into the form used mos tube is minimal
according to the formula 
wherein 
is such that in the worst case circuit rise time and fall time is equal, i.e., the inverter needs to be equivalent width to length ratio of the NMOS transistor and the PMOS transistor equivalent ratio of width to length of the inverter satisfy the relationship:
this refers to our calculated equivalent mos tube the aspect ratio of
the final this circuit we can get
3, a full adder inputs a, B, Cin, wherein a, B operand, Cin is a carry input, provided herein a full adder carry output as Cout.
(a) requested value of the truth table according to A, B, Cin of different logical, truth table listed;
Solution:
(B) obtained according to the truth table on Q, the following components select the correct number of CMOS static circuits spliced into a mirror carry adder circuit.
Solution:
as much as possible so that a set of output 0, output 1 as a group, as shown:
