# Taught himself 6week, pre hung up, did a test done P0 course, the felt understanding of the finite state machine concept, particularly involve timing is still very vague; abstract state is not enough skilled; implement logisim and Verilog It is also problematic. Online targeted logisim topic seems to be little, bloggers fear P0 hung up, so do do a study notes, share some understanding of the finite state machine, if there is something wrong place please correct me. I found an error will be updated.
Logisim in FSM (P0.L0.Q4)
Abstract states:
It should be noted that the current state / sub-state and the input is not the same, not to be confused with the need to identify when the abstract state contains all the state and state transition diagram no logical error ; such as error, re-select a new state. As for how to abstract the state with fewer bits you may need to do a lot of questions summarized.
For example, this question is the status of the last two characters have been entered (a total of four binary), Sed [3: 0] and S [3: 0],
Determine a good state and input can use a state transition logisim construct the combinatorial logic block, the same token can be used to build the output combinatorial logic block logisim
About mealy type and Moore-type timing issues
The logical structure of a finite state machine, I believe we are very clear, I do not know can find resources online self-seeking or see cscore tutorial finite state machine, but there is one thing I want to talk about:
Input and output current corresponding to the current status within a time period, corresponding to the current input and the current state output. I think it is conceivable that the input signal in a clock cycle of the open interval be a constant, the clock edge only considered as a new output, equivalent to the external signal is stored in a register (reg type in Verilog)
I too dishes before been thought to understand, leading to build upon Mealy type output combinational logic block is always tangled together whether to register a stable output, of course, I had thought wrong.