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Reading this article, you will learn the following:
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Verify reference IC
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How to read
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What are we going to IC verification
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How to learn IC verification
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Some online tutorials SV and the UVM
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IC meeting to do some validation should also concern
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IC verification related to several public number
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Some resources Github
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IC verification related scripting books
Relative to the previous version updated the following:
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Most of the increase in the book buying links
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Deleted blog link, link resources increased github
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Deleted book EDA, an increase of Internet software programming book
Verify reference IC
"SystemVerilog verification, Second Edition"
《SystemVerilog for Verification, Third Edition》
Word evaluation:
The industry called "Green Book", as SystemVerilog entry books, but also for query syntax purposes. A friend recommended that students begin to see the Chinese version, there are some basic validation of the IC and then look at the English original.
"UVM combat, Zhang Qiang"
Word evaluation:
The industry called "White Paper", is the first Chinese book UVM, 90% of IC verification engineers are learning this.
"Hitchhiker's Guide to chip verification, Liu Bin"
Word evaluation:
Called the industry's "Little Red Book", published just this year, giant road Sang, from verifying theoretical ideas, SystemVerilog UVM to like everything.
《 Practical UVM step by step examples》
Word evaluation:
UVM advanced a book, there are many complex example, the code book https://github.com/Practical-UVM-Step-By-Step/Practical-UVM-Step-By-Step.
《A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition》
Word evaluation:
UVM an introductory book, written by Cadence employees.
《Advanced Verification Topics》
Word evaluation:
A book written Cadence verification, discuss some advanced topics UVM verification.
《ASIC/SOC Functional Design Verification》
Word evaluation:
The most comprehensive verification book, including SV, UVM, constrained random, assertions, functional coverage, the CDC verification, low power consumption verification, formal verification, the ESL validation, verification software and hardware combined, mixed verification, the SOC interconnect verification.
《SystemVerilog Assertions and Functional Coverage》
Word evaluation:
A good introductory book asserts.
How to read
It is said that a lot of books, reading endless. Some people say, read a book, or do not know how to take environmental writing Case.
why? Not for reading and reading.
The book is more like a tool, in doing the project, the experience will not go read the relevant sections, the effect will be better.
What are we going to IC verification
IC verification do like taking pictures, the camera is a verification tool. Photo shoot is good, mainly photos presented beauty, abstract or record of practical significance. The camera device is a feature phone, or SLR is not so important.
IC verification is doing the same, using the verilog hair incentives, or C, or UVM is not so important. It is important to find the bug, reduce costs taped or failure to do the ECO.
So how do you find out more about bug, how to prove there is no bug RTL, how to find easier and faster bug? These are the IC verification of research.
How to learn IC verification
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To lay the foundation, SV and syntax should be familiar with UVM
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The transformation of existing verification environment
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Complete verification environment
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Continue to improve (this step loop N times)
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The introduction of new authentication method, continue to improve (this step loop N times)
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The method of the invention a new authentication or ideas
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Then you are already experts in the IC Verification
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Then you ought to share ideas IC verification, lifting the lower level of the industry
Some online tutorials SV and the UVM
Devaluation "verification Academy" , written by Mentor, there Cookbook, there are video tutorials.
https://verificationacademy.com/
"Verification guidance" , including SystemVerilog tutorials, UVM tutorials, SystemC tutorials.
https://www.verificationguide.com/p/home.html
"ASIC World" of SV course , said that the site has more than 3 million monthly page views.
http://www.asic-world.com/systemverilog/tutorial.html
doulos Tutorial
https://www.doulos.com/knowhow/sysverilog/
https://www.doulos.com/knowhow/sysverilog/uvm/
UVM candy lovers Tutorial
http://cluelogic.com/category/uvm/
http://cluelogic.com/2011/07/uvm-tutorial-for-candy-lovers-overview/
https://github.com/cluelogic/uvm-tutorial-for-candy-lovers
chipverify
https://www.chipverify.com/system-verilog/system-verilog
https://www.chipverify.com/uvm/uvm-tutorial
etc. tutorial
http://uvmtutorial.com/
UVM Tutorial
http://www.testbench.in/UT_00_INDEX.html
IC meeting to do some validation should also concern
DVCon（https://dvcon.org）
Design and Verification Conference, sponsored by the Accellera IC DV seminars worldwide. DVCon-US has been held 20 years, DVCon-China has organized two circles. Professionals are participating in the industry, or share experiences IC verification, validation or showcase the latest technologies and methods.
DAC（https://www.dac.com）
Design Automation Conference, it was called Oscar EDA industry. The first community began in 1964, it has held a total of 55 circles. Each year more than 1000 companies or organizations in the DAC, or release a new product, or to discuss cutting-edge technology.
CDNLive
CDNLive Assembly is an annual global user conference, organized by the tour company Cadence. Worldwide more than 6000 engineers here to share design results. In China Shanghai station, dozens of well-known experts and Cadence IC design tools company will design experts from overseas, with the majority of Chinese IC engineers on-site face to face exchanges by a wonderful speech.
SNUG
SNUG (Synopsys User Group) is an annual Synopsys Synopsys user activity in the world's major market areas held to summarize the successful experience of using Synopsys tools in the process by the user, in the form of papers submitted to the Organizing Committee of Synopsys users, aimed at Synopsys design tools for users to use to build an environment of open communication platform. To participate in this activity Synopsys users to communicate and exchange, being useful inspiration in the design concept and methodology.
These seminars concern, not only because the meeting can learn to share experiences with your peers, paper, technology, and more importantly, know more counterparts, make more friends.