1, on how to use fifo and Bram .
(1) I need someone to give me the exact argument why you need people to tell? Summarize how the documentation? Timing diagram.
(2) what others have provided information.
1 ① , there are a few signal lines, each signal line has any effect.
② the timing corresponding to the respective signal lines. We need to test validation.
2 , the timing for the verification test mode:
( 1 ) Verification
Corresponds to the data output enable signal. See the reverse order and outputs corresponding data.
（2）
How to do verification? Positive sequence and reverse design verification.
The timing diagram, a timing chart of positive sequence design, what makes the energy condition, the output data.
The output, verification reverse enable signal, or to the output data is consistent with the design of the signal.
For the inconsistency of how to analyze
1, the reason is not FIG.
(1) Check the enable signal (the amount of data is not satisfied), such as ADV7179 needs of each figure has a certain area and the video blanking active area, and if not not shown in FIG.
(2) measuring the output voltage data. Analog video data is output voltages 1.2V approximately. In the output data, the field signal is a negative level, only but obviously there is a high to low voltage and the data is not the same waveform is blanking area. After the addition of a push three data output wrong voltage, resulting in no data output.
(3) an output waveform diagram: comprising a peak, the clock frequency, the output frequency of the voltage data.
2, shake FIG cause chaos in FIG.
Mismatch (1) the amount of data. The main problem will cause an abnormal image display output section. As the amount of data which needs to rely on experience testing. Testing should generally start to finish to see whether a picture output can match the timing design.
(2) clock is not accurate. The main problem will lead to chaos flash the whole map, but also will become erratic.
3 , after finding the problem, how to solve.
1 , the overall analysis, verification portion investigation.
For specific questions, the overall analysis of the possible causes. Verify a single variable, the most important thing is to function parameters and timing and design coincide.
Skill points:
1 , for verilog , important to understand blocking and non-blocking assignments.
2 , at the same clock, a counting register, an enable signal to a next shot delay.
Back to the beginning, and how to understand the design and function of timing indicators, and different designs have different needs and equipment requirements. For example 7179 required output even lines together. Max9218 claim matching chip including a timing matching, matching like rising and falling edges. In normal use,
Related: different chip, to understand the design principles, and then to understand why this design, the final will know why should such a design. For example, why the chip needs powdown , MAX9218 and MAX9247 , are matched chips, so to match the requirements of the clock. Because there are transmission delays, all have a 90 phase difference of degrees.