FPGA study notes_image processing 4_FPGA implementation of gray-scale image mean filtering algorithm

FPGA study notes

Image processing algorithm

1. 灰度图像均值滤波算法
   1.1 原理
   1.2 FPGA实现灰度图像均值滤波算法

1. Grayscale image mean filtering algorithm

1.1 Principle

• Mean filtering : linear filtering, neighborhood averaging method.

• Principle : Use the average value to replace each pixel value in the original image. That is, find N pixels f(x,y) centered on the target pixel (x,y), and then use the average value of these N pixels to replace the original target pixel as the point g(x,y) of the processed image )=(1/N)(∑f(xi,yi)).

• Disadvantages : Can not protect the details of the image very well, make the image blurred, and can not remove the noise points well.

1.2 FPGA implementation of gray-scale image mean filtering algorithm

• Project goal:
  De-noise processing of color pictures through gray-scale processing, mean filtering algorithm, and display them on the TFT display through FPGA.

• FPGA implementation steps :

  1. Form 3*3 matrix pixels
  2. Find the sum of the pixels of 8 points in the surrounding neighborhood.
  3. Shift the result 3 places to the right (equivalent to dividing by 8) to get the result.

• FPGA implementation method :
  Methods (2 types): 1. Form the monochrome channel through the R/G/B channel and enter the average filter to achieve the average filter of the grayscale image. 2. Convert the RGB image to the Ycbcr image, and the Y channel enters the average Filter, realize the mean filtering of gray image.

  1. Through the R/G/B channel to form a monochrome channel into the average filter, realize the average filter of the gray image
     

  2. Convert RGB image to Ycbcr image, Y channel enters the mean filter, realize the mean filter of gray image
     

• Project component modules:
  ① pll: Generate the clock required for the project: 1. SDRAM controller clock; 2. SDRAM clock signal; 3. TFT screen controller clock
  ② uart serial port protocol (uart_rx, uart_tx)
  ③ read FIFO
  ④ write FIFO
  ⑤ SDRAM Control module
  ⑥ TFT screen control module
  ⑦ Gray processing, average filter module

• Verilog code

/*
 - 形成3*3矩阵像素
 - 求周围邻域8个点的像素之和
 - 将结果右移3位(相当于除8)，得到结果。

*/
module mean_filter_r0(
	input				clk,
	input				rst_n,
	
	input	  	[15:0] 	data_in,//输入像素
	input				data_in_en,//lcd显示区使能信号
	
	output	reg	[15:0]	data_out,//输出像素
	output	wire		data_out_en
);
	
	wire	[15:0]	r0;
	wire	[15:0]	r1;
	wire	[15:0]	r2;
	
	reg	[15:0]	ro_c0;
	reg	[15:0]	ro_c1;
	reg	[15:0]	ro_c2;
	
	reg	[15:0]	r1_c0;
	reg	[15:0]	r1_c1;
	reg	[15:0]	r1_c2;
	
	reg	[15:0]	r2_c0;
	reg	[15:0]	r2_c1;
	reg	[15:0]	r2_c2;
	
	reg				de_reg0;
	reg				de_reg1;	
	reg				de_reg2;
	wire	[18:0]	add_out;
//----3line pixels-----------------------------------	
	shifter3_3	shifter3_3(
		.clken(data_in_en),
		.clock(clk),
		.shiftin(data_in),
		.shiftout(),
		.taps0x(r0),
		.taps1x(r1),
		.taps2x(r2)
	);
//-------------------------------------------------
//----3*3 matrix pixels from image-----------------
//----r0-------------------------------------------
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			ro_c0	<=	16'd0;
			ro_c1	<=	16'd0;
			ro_c2	<=	16'd0;
		end
		else if(data_in_en)begin
			ro_c0	<=	r0;
			ro_c1	<=	ro_c0;
			ro_c2	<=	ro_c1;		
		end
	end
//----r1-------------------------------------------
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			r1_c0	<=	16'd0;
			r1_c1	<=	16'd0;
			r1_c2	<=	16'd0;
		end
		else if(data_in_en)begin
			r1_c0	<=	r1;
			r1_c1	<=	r1_c0;
			r1_c2	<=	r1_c1;		
		end
	end
//----r2-------------------------------------------
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			r2_c0	<=	16'd0;
			r2_c1	<=	16'd0;
			r2_c2	<=	16'd0;
		end
		else if(data_in_en)begin
			r2_c0	<=	r2;
			r2_c1	<=	r2_c0;
			r2_c2	<=	r2_c1;		
		end
	end
//-------------------------------------------------
//----timing --------------------------------------
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)begin
			de_reg0	<=	1'd0;	
         de_reg1	<=	1'd0;
         de_reg2	<=	1'd0;
		end
		else if(data_in_en)begin
			de_reg0	<=	data_in_en;
         de_reg1	<=	de_reg0;
		   de_reg2	<= de_reg1;
		end
	end
	assign	data_out_en = de_reg2;
//-------------------------------------------------
//----add------------------------------------------
	add_paral	add_paral(
		.clken(data_in_en),
		.clock(clk),
		.data0x(r0),
		.data1x(ro_c0),
		.data2x(ro_c1),
		.data3x(r1),
		.data4x(r1_c1),
		.data5x(r2),
		.data6x(r2_c0),
		.data7x(r2_c1),
		.result(add_out)
	);
//-------------------------------------------------
//----divide 8-------------------------------------
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			data_out	<= 16'd0;
		else if(data_in_en)
			data_out	<= add_out[18:3];
		else;
	end
endmodule

• Project result
  5-inch TFT capacitive touch screen
  Image: 800*480 pixels
  (1). (Yiyanqianxi^^) Original network image:
  
  (2). FPGA display original image:
  (3). FPGA grayscale processing image:

(4). FPGA average filter diagram:
project result analysis:

• Compared with the original image and the gray-scale processed image, the image is obviously more blurred after the mean filtering, and it is verified that the mean filtering cannot protect the details of the image very well when denoising the image.

---

Reference materials: "FPGA System Design and Verification Practical Guide"
[Note]: Personal study notes, if there are mistakes, please feel free to enlighten me, this is polite~~~

---