Detailed substantially regular PCB Altium

EDITORIAL:
This article aims to summarize the backup, to facilitate future inquiries, as is the personal summary, if wrong, please correct me; in addition, most of the content from the Internet, books, and various manuals, should please inform the infringement, immediately delete posts to apologize.

Adaptation of smaller rule, put the higher priority is provided.

First, the table of contents

• Electrical (ERC): safety distance, wire mesh connectivity
• The Routing (wiring): width, shape and size of the vias, the wiring topology, the wiring layer, packaging line like
• SMT (Surface Mount (SMT)): number of pads required patch element
• Mask (Mask): solder paste and extensions
• Plane (inner layer and plated copper): the inner layer and the plated copper and the connection pad
• Testpoint (Test Point)
• Manufacturing (processing): pore size, pad, screen printing, and the solder resist and the relationship
• HighSpeed ​​(high speed signal): cross talk, length, length distribution, the number of vias and other high-speed signal related to
• Placement (placing): component placement and spacing member
• SignalIntegrity (signal integrity): trace impedance and high-speed signal overshoot, slew rate, etc.

Second, the contents

Electrical (electrical design rules)

1. Clearance (safety distance) is arranged in the layout of copper traces, a minimum distance, between the pad and the wire, and the lead wires between the pad and the pad member between the PCB board.
2. Short Circuit (short-circuit) is provided on the short-circuit area setting option whether to allow cross-circuiting wire circuit. The default does not allow short circuit, namely deselect Allow Short Circuit complex options.
3. Un-Routed Net (unrouted nets) option field is provided to specify a network, check whether the network cabling successful, if unsuccessful, will remain connected with the fly line.
4. Un-Connected Pin (not connection pins) provided the specified options area network checks whether all the connection elements are pins.

Routing (routing design rules)

1. Width (conductor width) of the width of the wire locale option has three values ​​can be set for, respectively Max width (maximum width), (optimal width), Min width (minimum width) three values ​​Preferred Width. The system default value of the conductor width 10mil, click directly input a value to change each entry. Here use system default settings 10mil lead width.
2. Routing Topology (wiring topology rules) set options area topology rules defined constraints of wiring topology logic is employed. AD is a commonly used statistical routing constraints shortest logical rules.
   Select the type of topology options from the Topology drop-down menu.
   AD cabling topology provides the following rules:
   ① Shortest (shortest) rule setting minimum rules that define the shortest connection option is to connect all the nodes of the rules in the wiring.
   ② Horizontal (horizontal) level rule setting rule setting that uses the minimum level of the connection node of the connection rule.
   ③ Vertical (vertical) disposed vertically rule setting rules and mining it is connected to all the nodes, the shortest wiring rules in the vertical direction.
   ④ Daisy Simple (simple daisy) set the rules simple daisy rule settings. It uses a communication using the chain rule, from one point to another for all communication nodes, and connect the shortest.
   ⑤ Daisy MidDiven (Daisy midpoint) Daisy midpoint rule set rule set. The select a rule the Source (point source), which communicates to all nodes to the left of the center, and the shortest connection.
   ⑥ Daisy Balanced (Daisy balance) balance rule setting the rules set up daisies. It also select a source point, all the average number of intermediate nodes into groups, the groups are all connected to a source point, and the shortest connection.
   ⑦ Star Burst (star) rule setting a star rule settings. This rule is also used to select a source point in a star connection to another node, and the shortest connection.
3. Routing Priority (priority line) rule options area is provided for setting the routing priority order, in the range from 0 to 100. The larger the value, the higher the priority.
4. Routing Layers (FIG wiring rules) the rule is provided a wiring board guide wire alignment method. Includes top and bottom wiring layers, choose to allow alignment layer.
   AD offers 11 kinds of wire moves. Various wirings method: Not Used without the wiring layer; Horizontal layer wiring the horizontal direction; Vertical vertical direction of the wiring layer; Any arbitrary direction of the wiring layer; 1.0 Clock wiring layer by the one o'clock; 2.0 clock according to the wiring layer is a two o'clock; 4.0 clock wiring layer by the four o'clock; 5.0 clock the wiring layer according to the five o'clock position; 45Up the wiring layer is 45 ° upward direction, 45Down to the layer the method of the wiring 45 °; fan Out the wiring layer in a sector manner. For the default case where double-sided, using the other surface side of the wiring employed Horizontal Vertical embodiment mode.
5. Routing Corners (corner) area setting option can wirings 45 ° corner corners, 90 ° corners and rounded corners three.
6. Routing Via Style (through hole) is provided for setting the size of a wiring rule in the guide hole.
7. Fatout Contrl (fan-out wiring)
8. Differential Pairs Routing (using a differential pair of wires)

SMT (surface mount type design rules)

1. SMD To Corner SMD: SMD pads of the minimum spacing rule leads corner.
2. SMD To Plane: SMD pads and the power supply layer through the hole minimum spacing rule.
3. SMD Neck-Down: SMD pad necked rate rules. Development of joint width ratio of the width to the connection line.

Mask (Class shield design rules)

1. Solder Mask Expansion: shrinkage of the solder mask rule.
2. Paste Mask Expansion: fluxing amount of shrinkage rule layer.

Plane (power supply layer rules)

1. Power Plane Connect Style: a power supply layer connection type rule.
2. Power Plane Clearance: a power supply layer security regular spacing.
3. Polygon Connect Style: copper pads and connection type rule.

Test Point (test point rule)

1. Test Point Style: test point style rules.
2. Test Point Usage: Use test point rule.
3. Assembly Test Point Style: assembly test point style rules.

Manufacturing (PCB system board rules)

1. Minimum Annular Ring: minimum width of the copper ring pad rules to prevent pad off.
2. Acute Angle :( lead angle) at an acute angle limiting rule, not less than 90 °.
3. Hole Size: aperture limit rule
4. Layer Pairs: matching layer disposed rules set all the drilling electrical symbols (pads and vias) of the initial layer and a stop layer, using the design guidelines of the blind hole.
5. Hole To Hole Clearance: inter-hole spacing E Gui
6. Minimum Solder Mask Sliver：
7. Silkscreen Over Component Pads: screen printing and pad pitch rule Component
8. Silk To Silk Clearance: screen printing a regular spacing
9. Net Antennae: network antenna rule

High Speed ​​(high-frequency circuit Rules)

1. ParallelSegment: parallel line pitch copper film limiting rule
2. Length: network length limit rule
3. Matched Net Lengths: network matches the length rule
4. Daisy Chain Stub Length: chrysanthemum branch wiring length limitation rule
5. Vias Under SMD: SMD pads via the limiting rule
6. Maximum Via Count: rules limiting the maximum number of vias

Placement (element arrangement rule)

1. Room Definition: element defining a set of rules
2. Component Clearance: spacing limiting rule element
3. Component Orientations: the direction of element arrangement rule
4. Permitted Layers: Allow plies regularly arranged elements
5. Nets To Ignore: Network Ignore Rules
6. Hight: height rule

Signal Integrity (signal integrity rules)

1. Signal Stimulus: excitation signal rules
2. Undershoot-Falling Edge: negative overshoot limit rule under Chongchao
3. Undershoot-Rising Edge: positive overshoot limit rule under Chongchao
4. Impedance: Impedance limit rule
5. Signal Top Value: high-level signal Rule
6. Signal Base Value: Low Signals
7. Flight Time-Rising Edge: rise time of flight rules
8. Flight Time-Falling Edge: fall time of flight rules
9. Slope-Rising Edge: rising time rules
10. Slope-Falling Edge: fall time rules
11. Supply Nets: Power network rules

Third, the source

ORIGINAL ☜ poke me ah