Altium Designer (AD) software use record 05-PCB stack design

Altium Designer (AD) software use record 05-PCB stack design

1. Introduction of positive and negative layers

1. Positive layer (Signal)

The positive film is usually used in the signal layer of the wiring. The place where the wiring is made is a copper wire, and Polygon Pour is used to fill a large piece of copper.

2. Negative layer (Plane)

Negative film is just the opposite. It is the default copper plating, and the place where the line is routed is the dividing line, that is, after generating a negative film, the entire layer has been covered with copper. What needs to be done is to divide the copper plating, and then set the divided network.

3. Segmentation of the inner electrical layer

In AD, directly use Line and the shortcut key PL to divide. The dividing line should not be too thin, use 15mil or above.
To divide the copper pour, just use Line to draw a closed polygonal frame, and double-click the copper to set the network in the frame.

Both the positive and negative films can be used for the inner electrical layer, and the positive film can also be realized by wiring and copper plating.
The advantage of the negative film is that it is filled with a large block of copper by default. There is no need to rebuild when adding vias, changing the size of the copper, etc., which saves the time for PROTEL to re-calculate the copper. When the middle layer is used for the power layer and the GND layer, most of the layers are covered with large pieces of copper, so the advantage of using a negative film is obvious.

Suggestions and tips: It is recommended that the signal layer be processed in a "positive" way, and the power layer and GND layer be processed in a "negative" way, which can greatly reduce the size of the file data and improve the design speed.

2. Indentation design of positive and negative film layers

1. Negative film setting indentation

Design –> Layer Manager (shortcut key DK), select the negative film layer that needs to be set indented

Press F11 to pop up the property panel, find the Pullback distance column and fill in the value that needs to be indented.

Note: The stack is symmetrical by default. When setting the negative shrinkage value of the second layer, the third layer will also be modified to the same value synchronously; if no synchronous modification is required (one layer is GND, and the other layer is PWR), Uncheck Stack Symmetry to set different indentation values.

20H principle

The 20H principle means that the distance between the power layer and the formation is reduced by 20H, and H represents the distance between the power layer and the formation. Of course, it is also to suppress the edge radiation effect. EMI is radiated outwards at the edge of the board. The power layer is retracted so that the electric field is only conducted within the range of the ground layer, which effectively improves the emc. If the retraction is 20H, 70% of the electric field can be confined within the ground edge; if the retraction is 100H, 98% of the electric field can be confined.
We require the ground plane to be larger than the power or signal layer, which is beneficial to prevent external radiation interference and shield the interference from the outside world. Generally, when designing the PCB, shrinking the power layer by 1mm from the ground layer can basically meet the 20H principle.

The distance we shrink in is the distance of "20H" we said before. This H refers to the dielectric thickness between the power layer and the ground layer. The adoption of the "20H rule" means to ensure that the edge of the power plane is smaller than the edge of the 0V plane. At least the indentation is equivalent to 20 times the layer distance between the two planes.

However, due to the design of the stack, on some ordinary PCB boards, if the 20H is strictly met, the PCB wiring cannot be carried out, so the general processing method is to shrink the power supply GND by 1MM relative to the GND, so that the performance of our board is also guaranteed to a certain extent. .

We also need to note that our 20H principle can only have obvious effects under certain conditions.

1. The power plane should be inside the PCB, and the upper and lower layers adjacent to it are both 0V planes. The distance between these two 0V planes should be at least 20 times the layer distance between them and the power plane. .

2. The total number of layers of PCB should be greater than or equal to 8 layers.

Finally, the ground of the negative film is retracted by 20mil, and the power supply of the negative film is retracted by 60mil.

Then make a shielding ground via hole in the 1mm shrinkage tape, one 150mil.

2. Positive copper laying setting shrinkage

1. Set rules

Find the board frame layer in the PCB design interface, copy the board frame layer and paste it, convert it to keep-out-layer and disable the wiring layer tool – conversion – convert the selected element to keepout. Create a forbidden wiring layer consistent with the board frame layer.

DR finds Clearance, right-clicks and selects a new rule, as shown in the figure below: Set the minimum distance between the prohibited wiring layer and the copper laying (inner shrinkage value).

2. Re-lay copper

In the PCB design interface, select copper laying T->G->R, and select copper laying for relaying.
At this point, it's done.

3. The cascading design of AD

Design –> Cascade Manager (shortcut key DK)

1. Layers can be added, Signal is a positive film, and plane is a negative film.
2. The name of the layer can be modified by yourself. Generally, it is set to a name that is easy to identify.
3. Set the thickness of the board according to the stacked structure.
4. In order to meet the "20H" principle of design, you can set Negative layer indentation

4. Problems needing attention in stack design

1. Generally speaking, the stack design mainly follows two rules

1. Each wiring layer must have an adjacent reference layer (power or ground);

2. The adjacent main power supply layer and the ground layer should keep a minimum distance to provide a large coupling capacitance.

2. The stackup from two-layer board to eight-layer board is listed below for example explanation

1. Lamination of single-sided PCB board and double-sided PCB board

For two-layer boards, due to the small number of board layers, there is no problem of stacking. Controlling EMI radiation is mainly considered from wiring and layout;

The problem of electromagnetic compatibility of single-layer boards and double-layer boards is becoming more and more prominent. The main reason for this phenomenon is that the area of ​​the signal loop is too large, which not only produces strong electromagnetic radiation, but also makes the circuit sensitive to external interference. To improve the electromagnetic compatibility of the circuit, the easiest way is to reduce the loop area of ​​the key signal.

Key signals: From the perspective of electromagnetic compatibility, key signals mainly refer to signals that generate strong radiation and signals that are sensitive to the outside world. Signals that can generate strong radiation are generally periodic signals, such as low-order signals of clocks or addresses. Signals sensitive to interference are those analog signals with low levels.

Single and double-layer boards are usually used in low-frequency analog designs below 10KHz:

1) The power supply traces on the same layer are routed radially, and the sum of the lengths of the lines is minimized;

2) When running the power supply and ground wires, they should be close to each other; lay a ground wire next to the key signal line, and this ground wire should be as close as possible to the signal line. This forms a smaller loop area and reduces the sensitivity of differential mode radiation to external interference. When a ground wire is added next to the signal line, a loop with the smallest area is formed, and the signal current will definitely take this loop instead of other ground wire paths.

3) If it is a double-layer circuit board, you can lay a ground line along the signal line on the other side of the circuit board, close to the bottom of the signal line, and the line should be as wide as possible. The loop area formed in this way is equal to the thickness of the circuit board multiplied by the length of the signal line.

2. Lamination of four-layer boards

1. SIG－GND(PWR)－PWR (GND)－SIG；
2. GND－SIG(PWR)－SIG(PWR)－GND；

For the above two stackup designs, the potential problem is for the traditional 1.6mm (62mil) plate thickness. The layer spacing will become very large, which is not conducive to controlling impedance, interlayer coupling and shielding; especially the large spacing between power ground layers reduces the board capacitance and is not conducive to filtering noise.

For the first solution, it is usually applied to the situation where there are many chips on the board. This solution can get better SI performance, but it is not very good for EMI performance, and it is mainly controlled by routing and other details. Main attention: the ground layer is placed on the connected layer of the signal layer with the densest signal, which is conducive to absorbing and suppressing radiation; increasing the board area reflects the 20H rule.

For the second solution, it is usually applied to occasions where the chip density on the board is low enough and there is enough area around the chip (to place the required power supply copper layer). In this scheme, the outer layer of the PCB is the ground layer, and the middle two layers are the signal/power layer. The power supply on the signal layer is routed with wide wires, which can make the path impedance of the power supply current low, and the impedance of the signal microstrip path is also low, and can also shield the inner layer signal radiation through the outer layer. From an EMI control point of view, this is the best 4-layer PCB structure available.

Main attention: The distance between the signal and power mixed layers of the middle two layers should be opened, and the routing direction should be vertical to avoid crosstalk; the board area should be properly controlled to reflect the 20H rule; Arranged under the power supply and grounding copper island. In addition, the copper on the power or ground plane should be interconnected as much as possible to ensure DC and low frequency connectivity.

3. Lamination of six-layer board

For the design with high chip density and high clock frequency, the design of 6-layer board should be considered, and the stacking method is recommended:
1. SIG-GND-SIG-PWR-GND-SIG;

For this scheme, this stacking scheme can get better signal integrity, the signal layer is adjacent to the ground plane, the power plane and the ground plane are paired, the impedance of each trace layer can be well controlled, and the two The formations are good at absorbing magnetic field lines. And it can provide a better return path for each signal layer when the power supply and the ground layer are complete.

2.GND－SIG－GND－PWR－SIG －GND；

For this kind of scheme, this kind of scheme is only suitable for the case where the device density is not very high. This kind of stack has all the advantages of the above stack, and the ground planes of the top and bottom layers are relatively complete, which can be used as a better shielding layer. to use. It should be noted that the power layer should be close to the layer that is not the main component surface, because the bottom plane will be more complete. Therefore, the EMI performance is better than the first solution.

Summary : For the six-layer board solution, the distance between the power layer and the ground layer should be minimized to obtain good power and ground coupling. However, with a plate thickness of 62mil, although the layer spacing has been reduced, it is still not easy to control the distance between the main power supply and the formation to be very small. Comparing the first scheme with the second scheme, the cost of the second scheme will be greatly increased. Therefore, we usually choose the first option when stacking. When designing, follow the 20H rule and mirror layer rule design.

4. Lamination of eight-layer board

1. Due to poor electromagnetic absorption capacity and large power supply impedance, this is not a good stacking method. Its structure is as follows:

1.Signal 1 component surface, microstrip routing layer

2.Signal 2 internal microstrip wiring layer, better wiring layer (X direction)

3.Ground

4.Signal 3 stripline wiring layer, better wiring layer (Y direction)

5.Signal 4 stripline wiring layer

6.Power

7. Signal 5 internal microstrip routing layer

8.Signal 6 microstrip routing layer

2. It is a variant of the third stacking method. Due to the addition of the reference layer, it has better EMI performance, and the characteristic impedance of each signal layer can be well controlled.

1.Signal 1 component surface, microstrip wiring layer, good wiring layer
2.Ground formation, better electromagnetic wave absorption capacity
3.Signal 2 stripline wiring layer, good wiring layer
4.Power power supply layer , and the underlying stratum constitute excellent electromagnetic absorption
5.Ground stratum
6.Signal 3 stripline routing layer, good routing layer
7.Power stratum, with large power supply impedance
8.Signal 4 microstrip routing layer , a good trace layer

3. The best stacking method, due to the use of multi-layer ground reference planes, it has very good geomagnetic absorption capacity.

1.Signal 1 component surface, microstrip wiring layer, good wiring layer
2.Ground formation, better electromagnetic wave absorption capacity
3.Signal 2 stripline wiring layer, good wiring layer
4.Power power supply layer , forming excellent
electromagnetic absorption with the underlying
strata , a good trace layer

For how to choose how many layers of boards to design and what method to use, it depends on many factors such as the number of signal networks on the board, device density, PIN density, signal frequency, and board size. For these factors we have to consider comprehensively.

The more the number of signal networks, the greater the device density, the greater the PIN density, and the higher the frequency of the signal, the multi-layer board design should be used as much as possible. For good EMI performance it is best to ensure that each signal layer has its own reference layer.