Development of PowerPC processors can be divided into two stages: AIM (Apple-IBM-Motorola) alliance stage and Power.org stage, the instruction set is not until 2004 before the formation of the first version of the Power ISA 2.01, now in its Power ISA2.06, added virtualization, polynuclear other functions, and differentiation of the embedded (Book-E) and the two branches of the server. PowerPC processor, it can also be divided into classic PowePC processor and Book-E processor.
The main difference between the classic PowerPC processor and Book-E processor that MMU, and startup mode exception vector address:
1. The former supports real-address mode, three kinds of block and page mode address translation mode, while the latter only supports the enhanced mode of variable length page address.
2. After starting the former will immediately jump to the reset exception vector (0x100 or 0xFFF00100) into the real address mode, and performing, while the latter jump to the last four bytes of effective address space (0xFFFFFFFC) performed at the processor and after the completion of the corresponding work MMU configuration default mapping of effective address of the last 4K address space to come out of this address space execution.
3. The former exception vector address is fixed, the latter may be configured each by IVPR exception vector address registers and IVORn.
PowerPC is a classic representative of IBM and Motorola / Freescale's 60x family of processors, including Motorola / Freescale's MPC8XX / MPC82XX / MPC83XX / MPC86XX / MPC5XXX series and Motorola / Freescale / IBM's 74xx / 750 series. Book-E processors include the IBM / AMCC (APM) and the PPC4XX Motorola / Freescale QorIQ series and the series PPC85XX.
A further description please refer to:
1.Programming Environments Manual for 32-Bit Implementations of the PowerPC Architecture
2.Book E: Enhanced PowerPC Architecture
3.Power ISA V2.06
Reproduced in: https: //www.cnblogs.com/EmbeddedLiving/articles/2011674.html