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Chapter X system clock and timer
10.1 S3C2440 system clock and power management module
Clock power management module comprisingPart 3：
- Clock control
- USB control
- POWER control
Clock control logic required to produce S3C2440 clock signal ,include：
- FCLK CPU frequency of use
- HCLK AHB bus device used
- PCLK APB bus device used
Internal S3C2440 has two PLL (Phase Locked Loop) :
- Corresponding FCLK, HCLK, PCLK
- Another use of the corresponding USB (48M)
For the power control logic unit S3C2440 the power management module corresponding toFour modes：
- NOMAL mode
- SLOW mode: external clock
- IDEL Mode: FLCK CPU clock is turned off
- SLEEP mode: the internal power supply is disconnected
10.2 PWM and timers
There S3C2440A5 16The timer , the timer 0、1、2、 3has the PWM .
10.3 Real Time Clock
10.4 Watchdog Timer
Note: After this update will stop once the book study notes, transferred to another set-learning courses!
Note: After this update will stop once the book study notes, transferred to another set-learning courses!
Note: After this update will stop once the book study notes, transferred to another set-learning courses!