MCU internal structure
The microcontroller is an integrated circuit chip using VLSI technology is the central processing unit CPU having a data processing capability, random access memory RAM, a read only memory ROM, a variety of I / O ports and interrupt system, timer / counter, function (display driving circuit may further include a pulse width modulation circuit, an analog multiplexer, a / D converter circuit, etc.) into a small but complete microcomputer system including a silicon chip
classification:
- 1, general-purpose
press scope microcontroller (Microcontrollers) to distinguish. For example, universal type 80C51 microcontroller, which is not designed for some specific purposes; microcontroller is dedicated for a certain products even a product designed and manufactured, for example, to meet the requirements of the electronic thermometer, integrated in the on-chip ADC interface functions temperature measurement and control circuit. - 2, bus
by the microcontroller (Microcontrollers) to distinguish whether the parallel bus. MCU bus generally provided with a parallel address bus, a data bus, a control bus, these pins extend parallel to the peripheral device through the serial port can be connected with the microcontroller, in addition, many microcontrollers have been framed required peripheral device and peripheral interface within an integrated, it is possible in many cases do not extend parallel bus, and greatly reduce the chip size package cost provinces, such non-bus called microcontroller MCU. - 3, controlled
distinguished substantially according to the application field microcontroller (Microcontrollers). In general, industrial type addressing range, strong computing capacity; microcontrollers for appliances mostly special type, usually small package, low price, peripherals and peripheral interfaces high integration. Clearly, these are not the only classification and rigorous. For example, both the 80C51 microcontroller class is universal bus, may also be used for IPC.
Structure and function of the microcontroller 51
Basic features:
1.8 a data bus, 16-bit address bus of the CPU;
2. Boolean having processing capabilities and processing capability bit;
3. Harvard architecture, the program and data memory address space independently, to facilitate programming;
4 same address 64KB 64KB of program memory and a data memory;
5.0-8KB-chip program memory (not 8031, 8051, 4KB, 8052 has 8KB, 89C55 has 20KB);
the 6.128 byte data memory chip (8051, 256 bytes);
7.32 bi and the bit addressable I / O lines;
8. the two 16-bit timer / counter (8052 3);
9. a full duplex serial I / O interface;
a plurality of interrupt sources 10. the interrupt structure, having two interrupt priority;
the chip 11. the clock oscillator.
Features:
1. microprocessor (CPU) as a core;
2.CPU connected between the other components by a three bus.
Bus: refers to information and services for the transmission line can be a plurality of members.
Internal structure
SCM external structure
A total of 40 external pins as shown:
Pin Features
| Pin Number | Pin Name | Explanation |
|---|---|---|
| 1~8 | P1.0 ~ P1.7 | Port P1 |
| 9 | RST | A reset signal input terminal |
| 10~17 | P3.0 ~ P3.7 | Port P3, the port comprising a second functional |
| 18 | XTAL2 | A clock oscillator output, the output of the internal oscillator section |
| 19 | XTAL1 | A clock oscillator input, internal oscillator input section |
| 20 | GND | Power Ground |
| 21~28 | P2.0~P2.7 | Port P2 |
| 29 | PSEN (low) | When the external program memory fetches instructions from program memory or data read, this signal is valid |
| 30 | ALE / PROG (Low) | An address latch signal to access the external memory, the 8-bit address signal is latched low; no RAM, this pin is the output of the oscillator 6 frequency-divided signal |
| 31 | EA (low) / VPP | Program memory effective address, EA = 1 program execution starts from the inside; EA = begin program execution from an external 0 |
| 32~39 | P0.7 ~ P0.0 | Port P0 |
| 40 | VCC | Power positive |
1, P0 port structure
P0 port byte address 80H, bit address 80H ~ 87H.
As shown, a port from the latch, the input buffer, a multiplexer, a NAND gate, AND gate and a FET driving circuit.
P0-bit architecture:
- An input buffer
in the mouth P0, there are two three-state buffers, and tri-state gate has three states, i.e., its output may be high, low, while there is a high-impedance state (or referred to as prohibited state), to read the data output Q of the D latch, the latch needs to read the tristate control terminal of buffer effective, following a read buffer pin, to be read P0.X on the pins, but also so that the control terminal labeled "read pin" tri-state buffer is enabled, the data will be transmitted to a pin on the microcontroller's internal data bus. - D latch
constituting a latch, typically use a timing circuit, a trigger can hold one bit (i.e., having a holding function), the 32 I / O port lines of the microcontroller 51, is with a D flip-flops constituting the latch. In FIG. 1-4 D latch, D is a data input terminal, CP is the control terminal (control signal input terminal of timing), Q is an output terminal, Q is a non-inverted output terminal.
For the D latch speaking, when the D input has a signal input, a control terminal at this time if no signal CP (no arrival of timing pulses), then the data input terminal D is not transmitted to the output terminal Q and reverse output. If the timing control timing pulse terminal CP arrives, then the data input terminal D will be transferred to the Q and Q bar end. After transferring data over, the timing when the CP signal disappears timing control terminal, the output terminal also maintains the last data input terminal D (i.e., the latches the previous data). If the next pulse timing control signal arrives, then the data D transmitted again to the terminal before the terminal Q, thereby changing the state of the Q terminal. - Multiplexer
in the microcontroller 51, when the internal memory sufficient (i.e., does not require the outer expansion memory, memory mentioned here includes data memory and program memory), P0 port can be used as general purpose input / output ports (i.e., I / O) using, for 8031 (no internal ROM) of the microcontroller, or programs written exceeds the capacity of the internal memory of the microcontroller when the external memory is required, P0 port as address / data bus used. Then the multiplexer is selecting switch for selecting as a general I / O port is used as a selector switch address / data bus using a. Seen from Figure 1-4, when the multi-way switch is turned on and the lower end, P0 port as a normal I / O port; when the multiway switch is on the upper end, P0 port / data bus as the address.
When using the P0 port for external memory expansion and I / O, P0 port as a time-multiplexed address and data, the CPU transmission control signal, the door opening and the MUX hit the upper side, forming a push-pull configuration, the data signal can be directly read or output to an internal bus. When using P0 as a general purpose I / O, port P0 at this time is a quasi-bidirectional, the CPU transmission control signal, and blocking gates, to the pullup transistor off, hit the lower side of the MUX connected to the D flip-flop Q.
2, P1 port structure
P1 port byte address 90H, bit addresses 90H ~ 97H.
P1-bit architecture:
Different and P0, Pl only as a port I / O port to use, without the MUX, but the internal pull-up resistor, it does not require an external pullup resistor connected to the peripheral load, that P1, P2, P3 are the same.
3, P2 port structure
Byte address port P2 is A0H, address bits A0H ~ A7H
P2-bit architecture:
Port P2 as the I / O port lines as the P0 port usage and, when the internal switch in the other direction, that is, for address output, can output a high 8-bit address program memory or external data memory, and output port P0 together constitute the 16-bit lower address lines of the address.
4, P3 port structure
P3 port byte address B0H, address bits B0H ~ B7H.
P3 port with the other ports as the same I / O port lines when used, but also quasi-bidirectional, except that, for each bit port P3 another function, also known as a second function, functions will be used during Detailed explanation. When the port P3 as a general purpose I / O port, a second end of the quasi-bidirectional function remains high.
When the port P3 as the second function, the latch output Q = 1, as shown in the second function list to port P3:
5, pay attention
- (1) The system is in a non-expansion memory sheet, each of these four ports can be used as a general purpose quasi-bidirectional I / O port. System expansion memory in having an outer sheet, P2 port as a high 8-bit address lines, a bi-directional bus port P0, sharing as the low 8-bit address and data input / output line.
- (2) P0 port as a general-purpose bi-directional I / O port when used, must be an external pull-up resistor.
- (3) P3 except that port as a general purpose I / O port to use, but you have a secondary function. When the port P3 as a function of an output of a second, no longer as a general purpose I / O pins.
- (4) When the port P0 ~ P4 as an input, in order to avoid misunderstanding, all must first write the corresponding output latch 1, the FET is turned off, and then read port pins, for example the following procedure:
MOV Pl, 0FFH #
MOV A, P1
Program memory and data memory 51 are separate and distinct, internal data register in addition to the data register, a data register may also be extended, but with different access instruction coexist
Program register
When the EA pin high, the program uses the internal CPU registers, if the program exceeds the internal program memory space, the CPU will automatically re-reads the program code from the external program memory portion exceeds
Data register
~ 007FH 0000H
. 1, the register bank area
0000H ~ 001FH total of 32-bit register file address region
each group comprises registers R0, R1, R2, R3, R4, R5, R6, R7 eight registers, any time, both wherein a register group use only.
Switching register set, by a program status word (PSW) of RS1, RS0 to determine
RS0 RS1 address register bank
0 0 ~ 0000H 0007h the RB0
0 0008H ~ 000FH the RB1. 1
. 1 0 ~ 0017H 0010H the RB2
. 1. 1 001Fh the RB3 ~ 0018H
2, bit addressing area
0020H ~ 002FH 16-byte memory area is bit addressable region
disposed 20H memory address bits 5 to 1: SETB 20H.5
setting bit 5 set to 20H memory address is 0: CLR 20H.5
3, generally with the stack data area
80 is 0030H ~ 007FH byte data access and the general stack area
128B Special Function Register (SFR) between 0080H ~ 00FFH
special function registers
P0, P1, P2, P3
are the 451 input / output port addresses are 80H, 90H, A0H, and B0H.
P0 port: This 8-bit are open-drain outputs, each pin can drive 8 LS TTL load type; and no internal pull-up resistor, the output function is executed, the external pull-up resistor must be connected (10 kohm to ); to perform an input function, an output must be high, in order to read the external data port is connected; If the system is connected to an external memory, the address bus as P0 (A0 the A7) and a data bus (D0 D7) the multi-function pins.
P1 port: internal 30 kohm pull-up resistor, the output function is executed, without connecting an external pull-up resistor; 8 are the open-drain outputs, each pin can drive four LS TTL load type; To do input, the output must be high, in order to read the external data port is connected;
P2 port: internal 30 kohm pull-up resistor, the output function is executed, without connecting an external pull-up resistor; the 8 bits is an open-drain output, each pin can drive four LS TTL load type; to perform an input function, an output must be high, in order to read the external data port is connected; If the system is connected to an external memory, and the address lines of the external memory when more than 8, the port P0 as the address bus (A8 ~ A15) pins.
P3 port: internal 30 kohm pull-up resistor, the output function is executed, without connecting an external pull-up resistor; 8 are the open-drain outputs, each pin can drive four LS TTL load type; To do input, the output must be high, in order to read the external data port is connected;
P3 port other features:
P3 other function
P3.0 RXD serial port receive pin
transmits serial port pins P3.1 RTD
P3.2 INT0 INT0 interrupt input
P3.3 INT1 INT1 interrupt input
P3.4 T0 timer 0 input
P3.5 T1 Timer 1 input
P3.6 WR into the external memory control pin
P3.7 RD read external memory control pins
The SP
the SP stack pointer register as an address of 81H.
The DPL, DPH
the DPL and DPH is 8-bit data pointer register, which addresses are 82H, 83H. In terms of DPL is the lower 8 bits, the upper 8 bits of the DPH, to form a 16-bit data pointer register, referred DPTR, so the data will be addressed to the address of 64KB.
The PCON
the PCON as a power control register, which address bits 87H, whose function is to set the power supply mode of the CPU.
It is not a bit-addressable register. As shown:
the SMOD - - - GF0 General the GF1 the IDL the PD
Bit7 of bit6 bit5 bit4 bit3 bit2 bit1 bit0
wherein Members as follows:
the SMOD bit to bit rate multiplier. When the serial port operates in mode 1, mode 2, mode 3, and using a timer 1 for bit rate generator, if it is a 1, this bit rate is doubled, if it is 0, this normal bit rate.
GF1, GF0 general purpose bit flags, the user can set or clear these two flags. The two commonly used as an interrupt flag 8051 in the wake idle mode.
PD bit to power down mode bit. Is 1, enters the power down mode; is 0, and the power down mode.
IDL bit idle mode bit. 1 when entering idle mode; when 0, and the idle mode.
The TCON
the TCON timer / counter control register, an address of 88H
The TMOD
the TMOD a counter / count mode control register, whose address is 89H, and its function is the way it is provided
TL0, TL1, TH0, TH1
TL0, TH0 timer for the first group, the metering counter register, an address of 8AH, 8CH, the TH0 TL0 can be combined with the 16-bit timer / counter. TL1, a second set of timers TH1, the metering counter register, an address of 8BH, 8DH, the TH1 TL1 can be combined with 16-bit timer / counter.
The SCON
the SCON serial port control register, an address of 98H, whose function is to set the serial port and work sign.
SBUF
SBUF serial port buffer, which address 99H, which is formed by the use of the same two address registers, one register as a transmission data buffer, another register as the reception data buffer. As to how to distinguish between the same two address registers, depending on the instruction set, if the data transfer instruction, the data transfer to the automatic positioning of the buffer; if the receive data command, then automatically positioned to the reception data buffer. Revisit the strategy in detail later. IEs
IEs for the interrupt enable register, an address of A8H.
IP
IP interrupt priority register.
The T2CON
the T2CON Timer is the timer 2 / counter control register, whose address is C8H, its function is set dead starts Timer 2, the recording timer / counter overflows, and external interrupt trigger mode.
RCAP, of RCAP2H
RCAP, of RCAP2H capture register, an address of CAH, CBH. When the Timer 2 capture mode, if the input signal on pin T2EX (P1.1) have a high level to a low level, TL2 and TH2 contents will be loaded with RCAP RCAP2H, like the Timer 2 content catch into the same RCAP register.
TL2, TH2
TL2, TH2 third set of timers, counters the measurement register, an address of CCH, CDH, the TL2 and TH2 can be a combination of 16-bit timer / counter.
The PSW
the PSW is a program status word register of the CPU, an address of D0H, which reads as follows:
. 7. 6. 5. 4. 3. 1 0 2
the PSW CY the AC F0 RSl RS0 the OV P
PSW.7: Standard for the carry bit (CY), subtraction when a carry or dislocation, 1 will self-set, 0 otherwise.
PSW.6: Standard auxiliary carry bit (the AC), addition and subtraction operations for a carry or dislocation, 1 will self-set, 0 otherwise.
PSW.5: standard flag for the user, user-set.
PSW.4 and PSW.3: these bits are register bank select bits (RS1, RS0), which function in the following table.
RS1 RS0 register bank
0 the RB0 0
0 1 the RB1
1 the RB2 0
1 1 the RB3
PSW.2: Standard for the overflow flag (OV), run time, if an overflow occurs, 1, and 0 otherwise.
PSW.1: this bit is reserved, does not provide services.
PSW.0: Standard bit parity bit (P), 8051 using even parity, odd number if the ACC 1, 1, compared with an even number of 1 or 0.
The ACC
the ACC accumulator A register is also known, which address E0H.
B
address B register is F0H, A main function is to register with the multiplication or division. When multiplied, in the multiplier register B, and the calculation result, the higher 8 bits in the register B; time division operation, the divisor in the B register, and the result of the operation, and the remainder in the B register. If for multiplication / division, B register is also used as a general purpose register.
Gates
- AND gate
- OR
- NAND gate
- With or door
- XOR gate
- Combining circuit between the gate
TTL and MOS gates to achieve integration gate circuit
Register and latch
-
Trigger classification:
1, the basic RS flip-flop
2, the synchronous RS flip-flop, flip-flop D sync
3, master-slave RS flip-flop, master-slave JK flip-flop
4, Edge Trigger:
rising flop (D flip-flop, JK trigger)
falling-edge trigger (D flip-flop, JK flip-flop) -
Trigger logic function representation:
characteristic table, Carlo FIG characteristic equations, state diagrams, timing diagrams -
Introduced a variety of triggers
