Table of contents

program memory

ROM read-only memory, which stores instructions and is not lost after power failure

Program memory: ROM, EPROM (programmable read-only memory).

data storage

Common chip types include RAM (random access memory) and EEPROM (erasable programmable read-only memory).

As long as the control lines of different units are controlled, different data can be written to each unit --> use 8 wires or 16 wires to decode --> the eight wires that transmit data are common, called the data bus , the sixteen address lines are also common, called the address bus.

80c51 microcontroller

According to the function of the pin, it can be divided into three parts:

1. Power supply and crystal oscillator: ( crystal oscillator : in 80C51, crystal oscillator is usually used as the main source of internal clock)

·Vcc——Connect to the positive end of the power supply during operation and program verification.

Vss - ground.

· XTAL1 - on-chip oscillator inverting amplifier input.

· XTAL2 - the inverting amplifier output of the on-chip oscillator.

( An inverting amplifier is one in which the phase of the output signal is opposite to that of the input signal, and the gain is determined by the feedback network of the circuit)

For 80C51, when using an external oscillator, the external oscillation signal should be directly added to XTAL1, while XTAL2 is floating. In the internal mode, the clock generator divides the frequency of the oscillation pulse by two, such as the crystal oscillator is 12MHz, and the clock frequency is 6MHz. The frequency of the crystal oscillator can be selected within 1MHz-24MHz. The fine-tuning capacitor is about 30PF (as shown in the figure).

(Pulse divided by two:)

In 80C51 microcontroller, P0, P1, P2, and P3 are four 8-bit I/O ports that can be used to input/output data and control signals. Each I/O port contains 8 pins labeled P0.0-P0.7, P1.0-P1.7, P2.0-P2.7, and P3.0-P3.7

The structure diagram of 80c51 microcontroller is as follows:

There are four control lines:

➢RST
- VPD: backup power input terminal (when the power supply fails and the power supply drops to the lower limit, the backup power supply provides voltage to the internal RAM through this terminal to protect the data in the internal RAM from loss)
- Reset input signal, active high. When the oscillator is working, apply a high level on RST for more than two machine cycles to reset the device. ( The electronic device or system will clear all internal states and return to the predefined initial state when the high level is applied to RST for more than two cycles. )
➢/EA
- Vpp: programming voltage, the specific voltage value depends on the chip - off-chip program memory access permission signal, active low.
- /EA=1, select on-chip program memory (4KB for 80C51, 8KB for 80C52);
- /EA=0, the program memory is all off-chip regardless of whether there is program memory in the chip.
- When the EA line is in a high level state, the 80c51 will execute the internal program, that is, use the program stored in the on-chip ROM. Conversely, when the EA line is in a low state, the 80c51 will execute an external program, that is, use the program stored in the off-chip memory

ALE ( PROG : programming pulse) - address latch enable signal, output.
- When accessing off-chip memory or I/O, it is used to latch the lower eight-bit address to realize the isolation of the lower eight-bit address and data.
- Even if the external memory is not accessed, the ALE terminal still outputs a pulse signal at a fixed frequency (this frequency is 1/6 of the oscillator frequency). An ALE pulse occurs when accessing external data memory.
- ALE can drive 8 LS TTL loads.
- When programming the on-chip program memory, this pin is used to input the programming pulse PROG.
- In a computer system, the CPU needs to send the address of the data memory or other device to be accessed to the peripheral device through the address bus. In the process of sending the address, the CPU needs to ensure the stability and accuracy of the address signal to avoid errors during data transmission.
  
  To achieve this, the CPU sends a pulse signal to the peripheral device through the ALE control line, telling the device to send an address signal now. After the peripheral device receives this signal, it will latch the address into an internal address latch to ensure the stability and accuracy of the address signal
/PSEN —— off-chip program memory read strobe signal, active low.
- During an instruction fetch from the off-chip program memory, the contents of the program memory are sent to port P0 (data bus) every machine cycle when it is valid.
- It can drive 8 LSTTL loads.
- When the CPU needs to read instructions from the program memory, it will send the corresponding address to the program memory, and at the same time send a PSEN control signal to notify the program memory to prepare to transfer data (instructions) back to the CPU. After the program memory receives the PSEN signal, it transmits the data (command) back to the CPU, and automatically restores to the initial state after the transmission is completed

The 80C51 has three basic addressing spaces:

➢64 KB on-chip and external program memory addressing space; (determined by EA) on-chip program memory is read-only memory ROM
➢64 KB off-chip data memory addressing space;
➢256B (or 384B) on-chip data memory addressing space, including special function register addressing space.

In 80C51, there is an address indicator of a special data memory - the data pointer DPTR, which is used to access the off-chip data memory ( ERAM ). The data pointer DPTR is also a 16-bit register, so that the 80C51 has a 64 KB data memory expansion capability.

On-chip data memory structure diagram:

The following 7 specific addresses are reserved:

Reset 0000H~0002H (3 units)

External interrupt 0 0003H ~000AH (8 units)

Timer T0 overflows 000BH ~ 0012H (8 units)

External interrupt 1 0013H ~001AH (8 units)

Timer T1 overflow 001BH ~0022H (8 units)

Serial port interrupt 0023H ~002AH (8 units)

*Timer T2/T2EX 002BH~0032H (8 units, 80C52)

The part in red font is the five interrupt source addresses of 80C51 . During programming, an unconditional transfer instruction is usually set at the entry of these interrupts to make them turn to the corresponding interrupt service program segment for execution.

Interrupt system:

IE0 and IE1 are used as flag bits, indicating whether an interrupt occurs

Timing counter interrupt: When the timer counter overflows, IF0 or IF1 is set to 1, indicating that an interrupt occurs

interrupt function

When calling other functions in the interrupt function, it is necessary to ensure that the register set (0, 1, 2, 3) of the function is the same as the interrupt function

Timers and Counters

TMOD: Select the counting method

TCON

TH0: The high 8-bit count value register is used to store the high 8-bit count value of the timer counter.
TL0: Low 8-bit count value register, used to store the low 8-bit count value of the timer counter

PWM

display module

LCD1602 display

RS, when this pin is at a high level, the transmission operation of the data byte (that is, the byte displayed on the LCD1602 is used, and the data of the LCD1602 is 8 bits); when this pin is at a low level, it is the command byte (that is, the bytes used to set some working modes of LCD1602) transmission operation.

R/W, read and write selection terminal. When this pin is high level, it can read data from LCD1602, otherwise it can write data

E, the enable signal is actually the data control clock signal of LCD1602, and the data transmission to LCD1602 is realized by using the rising edge of this signal

As shown in the figure, not all addresses can be directly used to display character data, only 00-0F in the first line and 40-4F in the second line can be displayed, and other addresses can only be used for storage. When you want to display characters, you must first input the display character address, which is to tell the module where to display the characters.