There are two ARM instructions plurality of data transmission:
LDM: (load much) multiple data loaded will be loaded to the value of the register [address memory read, write multiple registers ]
STM: (store much) multiple data stores, the stored value of the register to the address { the value of the plurality of registers into memory ]
The main purpose: site protection, data replication, and other transmission parameters, a total of 8 modes (the foregoing four kinds of transmission for data blocks, four kinds of operations followed by the stack) as follows:
(. 1) IA: (Increase the After) after every transmission address plus 4, wherein the register from left to right, for example: STMIA R0, {R1, LR } preexisting R1, reload LR
(2) IB: (Increase Before) before each transfer address plus 4, supra
(3) DA: (Decrease After) after each address transfer Save 4, wherein execution of the register from right to left, for example: STMDA R0, {R1, LR} preexisting LR, R1 reload
(4) DB: (Decrease the Before) before each transfer address minus 4, supra
(5) FD: Full decrements the stack (4 Save address before each transfer)
(6) FA: Full stack is incremented (after each address transfer Save 4)
(7) ED: Empty decrements the stack (before each transfer address plus 4)
(8) EA: Increment empty stack (after each transfer address plus 4)
Note: wherein is STMMDB LDMIA and the corresponding transmission data block, STMMIA and the corresponding LDMDB
In operation of the stack and is STMFD LDMFD correspond, STMFA and the corresponding LDMFA
format:
LDM{cond} mode Rn{!}, reglist{^}
STM {cond} Rn fashion {!}, {^} Reglist
among them
Rn: a base register containing the start address of transfer data, Rn is allowed R15;
! : Indicates the last address written back into Rn;
reglist: range may comprise more than one register, with "," separated, such as {R1, R2, R6-R9}, the register in ascending order;
^: Not allowed to run in user mode and system mode
The transmission data block - Example:
LDR Rl , 0x10000000 = starting address of data transfer // 0x10000000
LDMIB Rl !, {R0, R4-R6} // load from left to right, corresponds to the LDR R0,10000004 LDR R4,10000008 ... ...
/ * Pre-increment transmission +4,
So address plus 4, R0 = 0X1000004 address in the content,
Address plus 4, R4 = 0X10000008 the contents of the address,
Address plus 4, R5 = 0X1000000C address in the content,
Address plus 4, R6 = 0X10000010 address in the content,
Because! Final address is written back in R1, R1 = 0X10000010 * /
LDR Rl , 0x10000000 = starting address of data transfer // 0x10000000
LDMIA Rl !, {R0, R4-R6} // load from left to right, corresponds to the LDR R0,10000000 LDR R4,10000004 ... ...
/ * When the transfer address plus +4,
So R0 = 0X10000000 address the contents of the address plus 4,
R4 = 0X10000004 the contents of the address, address plus 4,
R5 = 0X10000008 address the contents of the address plus 4,
R6 = 0X1000000C address the contents of the address plus 4,
Because!, The final address is written back to the R1, the so = R1 0X10000010 * /
The LDR Rl, = 0x10000000 starting address of data transfer // 0x10000000
LDR R4,=0X10
LDR R5,=0X20
LDR R6,=0X30
STMIB Rl, {} // R4-R6 loading from left to right, corresponds to the STR [R4], 0X10000004 STR [ R5], 0X10000008 .....
/ * Address plus +4 before transmission, so 0X10000004 = 0X10,0X10000008 address address = 0X20,0X1000000C address = 0X30 * /
LDR Rl, = 0x10000000 starting address of data transfer // 0x10000000
LDR R4,=0X10
LDR R5,=0X20
LDR R6,=0X30
STMIA R1!,{R4-R6 }
/ * Transfer after the address plus +4, so 0X10000000 address = 0X10,0X10000004 address = 0X20,0X10000008 address = 0X30, because the!, The final address is written back in R1, so R1 = 0X1000000C * /
Examples of the interrupt ( use STMDB LDMIA and protect the site, and then returns through register LR )
1. The first set stack sp, data storage register for later use stmdb
2. When an exception, will enter the break:
sub lr, lr, #4
// First lr-4, since the arm assembly line, lr = current pc + 8, since pc + 4 segment is not performed, so lr = (+ current. 8 PC) -4; STMDB !, {r0 of SP-R12, LR}
-4 // before each transfer, and from right to left storage register
// so the sp-4 = lr, sp-8 = r12, ... sp-56 = r0; because it is the last address written back to the sp, sp = sp-56!;
LR LDR, int_return = // return address provided
the p-LDR c, = EINT_Handle // into the interrupt service routine, if she would return calls pc = lr, you can perform int_return;
int_return: ldmia sp!, { r0-r12,pc }^
// each +4, left and right rear loading data into transfer register
// So r0 = sp, r1 = sp + 4, ... pc = sp + 52; because it is written back to the last address in sp, sp = sp + 56!;
// At this point, sp = sp + 56 equal to the initial value of the stack, pc = lr, then returns to the appropriate location before the error occurrence continue.
// ^ ^ represent copies the value spsr to cpsr, because of the need to restore the previous state of exception occurred after the exception return