课程背景Wuhan Science and Technology embedded Courses (www.embedhq.org). FPGA technology after 30 years of development, has now been applied to various fields, and is gradually becoming more and more technology-leading system-level solutions. Engaged in or about to engage in order to help FPGA design engineers FPGA technology as soon as possible to understand and master the methods and means of design, we design for an FPGA beginner this four-day course focuses on FPGA technology base, Verilog language and Embedded SOPC system design soft-core processor.
课程目标Familiar typical device type and construction FPGA
2. skilled FPGA design process and development method
3. The method of design master Verilog language
4. The master state machine design method
The master FPGA emulation and debugging methods
6. The skilled SOPC system design process
7. method II NIOS master hardware design system
8. the control system design software NIOS II
9. the master design definition from hardware components, drive design, software design and
debugging embedded soft core 10. master system
11. the master FPGA common Interface the design approach
12. Mastering associated development tools
师资团队[Liu]
● Wuhan embedded Senior Lecturer, Master of Engineering, Wuhan University, served as a well-known enterprise hardware project manager in Wuhan, 5 years of experience in the development of embedded systems, 3 years project management experience, 3 years of experience in the embedded trainers. Skilled FPGA-based UART, VGA interface circuit design, FPGA proficient in project design and development, master ISP, SIGNAL TAP and other advanced debugging methods, skilled application NIOSII. Familiar IC design process, skilled application related EDA design tools; mastering applications, the hardware design of the test circuit; familiar C51 microcontroller embedded processors and ARM, CPLD and FPGA programmable logic devices.
Specialty research: FPGA systems development, C51 microcontroller, the ARM system development and design, PCB high-speed drawing.
课程大纲
第一天Learning objectives
on the first day of the course will help students understand the basics of FPGA system design, so that students typically apply for FPGA and solutions, the typical model and structural characteristics have an in-depth understanding. Students will master the basics of Verilog language debugging methods and Modelsim's.
第二天Learning Objectives
course the next day to Verilog language-based learning, behavioral familiar with logic design methods, design methods to master the three-state machine and simulation, and lay a good foundation for the design of FPGA systems.
第三天Learning Objectives
third day of the course to the concept of SOPC system as the starting point, focusing on FPGA EDS solve architecture and hardware design flow solutions. Around soft-core processor, Avalon bus, and Peripheral Component three aspects of the hardware architecture of SOPC introduced. So that students SOPC project through simple, practical grasp EDS / XPS tool usage and basic hardware design process.
第四天Learning Objectives
fourth day curriculum-based software development and debugging. By the fourth day of learning, students should master the software development process NIOS II system and related tools, systems can be configured for different system requirements, and select or design the appropriate API interface for software development. With the contents of the first three days of lectures, master QSYS system hardware and software co-design design.
Detailed course see every day: http://www.embedhq.org/html/jingpin/fpga/2009/0519/49.html