MATLAB / Simulink HDL Quick Start
We will use examples to explain getting started with MATLAB/Simulink HDL.
To start this project, you first need to create a new Simulink containing Stateflow. Just click anywhere in the canvas and start typing into Stateflow.
You should now see the Stateflow icon on the canvas. Double-click the icon to edit.
Once in the chart editor, you can add states and transitions between states. To start, we create two states and name them "idle" and "LED". There are no conditions for conversion between them.
To add state transition conditions, double-click the transition and enter the required conditions.
Of course, a state machine can have Mealey and Moore outputs that occur as a function of the current state (Moore) or the current state and inputs (Mealey). In this example, declare the LED output as a Moore output and declare it in each state.
The final result is shown below.
Using the Model Browser we can define the inputs and outputs of the state machine. For the inputs, we keep them as the same types as Simulink, but need to define the outputs. Since LED requires three bits, we use type fixdt(0,3,0). This means that the vector is three bits wide, unsigned, and has no numeric fractional elements.
Also, check the "Execute (input) chart on initialization" option in the Model Explorer.
Navigate to the canvas above the chart. Here we need to add block IO and we will also add latency. In the canvas, start typing input or output to get the desired port.
You can also name the ports and set them to the correct type by double-clicking on the inputs and outputs.
Set sw_in to the same fixdt(0,3,0) as the previously declared output type. We use delays to add registers. To add additional delays, just type in the canvas.
To change the length of the delay, double-click the delay and change it to Delay 1.
The image below shows the complete chart.
Now we can generate RTL from it, but first we will create a testbench for it. Select all elements on the canvas, right-click it and choose Create Subsystem from Selection.
Add the step function and constants, set the block type used in the subsystem block, and make sure the sample time for discrete sampling is set to -1.
Right-click on the signal of interest and select Start recording the selected signal.
Open Model Explorer and set the model to discrete time with a fixed step timer.
Run the simulation and open the Data Inspector. You should see SW_ENB being set and the LED output going high after the next clock.
Now we can create the HDL and export it for use in Vivado. We can do this by right-clicking on the subsystem and selecting Generate HDL for Subsystem.
If you want to change the format of any generated HDL code (i.e. remove clock enablement), you need to select the Global Settings option from the HDL Code Generation tab.
After you generate the code, you will see a message in the MATLAB window where the code was generated.
This HDL can then be imported into a Vivado project. The generated code itself is actually readable and depends on how well we annotate the Simulink diagram. For example, I can name the state diagram and this will be reflected in the case statement name.
Three VHDL files are generated: the package containing the declarations, the actual source code implementing the state machine, and the top-level file.
Synthesized in Vivado, the final design required three flip-flops and two LUTs.
Of course, this is a simple example, but be able to learn the process so that you can use it for more complex applications.