I. Overview
I have been exposed to FPGA a lot recently. This time it is an FPGA with a zc706 chip. The development version looks like this. Basically, development is done by installing a combination of modules from the development version.
The Ethernet chip on the development version uses Marvell 881116R.
This article only verifies the instructions for controlling the Ethernet mode test, and does not include test results. If you need to test this project, you must first have an oscilloscope and test kit that can test the integrity of the Ethernet. Usually, if the company does not have a high-end oscilloscope, it can usually perform stress testing through iperf or chariot. Currently, I have a ready-made iperf program that can be executed on the Linux platform of the xilinx chip. If you need it, please send me a private message.
Two: Test
1. First, you need to understand the overview of the test module and the corresponding register configuration values in the Ethernet chip specification sheet. Here is the RTL8211E chip (basically the registers of the Ethernet configuration test mode are the same) as an example. The corresponding configuration of the registers in test mode can be viewed in the chip manual.
2. Directly download the Linux program of the PS part under xilinx. The convenience of this test is that you can directly use the Linux system provided by xilinx to operate the Ethernet register. First, download the Linux system blindly on the xilinx official website. First, you need to register on the official website. An account, scroll down on the AMD Zynq 7000 SoC ZC706 Evaluation Kit page to find rdf0287-zc706-pcie-trd-2015-4.zip and download it.
3. Unzip it directly after downloading, place all the files in prog_qspi in ready_to_test in SD, and use the SD card to start the board configuration.
4. To configure Ethernet, you need to use the serial port to connect the board, and then start the operation under the Uboot interface. First enter uboot mode, connect to the serial port, the baud rate is 115200, after starting the serial port and printing data, press the keyboard casually to start the terminal system and enter the uboot mode. In this mode, the input display is zymq-uboot>.
5. You can check the currently connected device and its address through the mdio command. No PHY address device is found when starting for the first time. When starting up for the first time, check that the PHY address is empty under uboot. You need to perform a ping operation. Ping an address at random, such as ping 192.168.100.100, and wait for the prompt host 192.168.100.100 is not alive. After executing mdio list again, the current Ethernet will be displayed. net.
6. You can see that the PHY chip is connected to address 7, and you can use mii dump 7 0 to view the data at address 0x00 of the register of the PHY chip at address 7, which is displayed in binary form. For example, the following figure shows 0001010010000000, which converted to hexadecimal is: 1140.
7. Test mode 1. In this mode, pulse template test, voltage fading test, and peak voltage test need to be tested. The template of the Ethernet test standard is as follows:
To configure test mode 1, you need to modify the following registers:
zynq-uboot> mii w 7 0 8100h
zynq-uboot> mii w 7 0 0140h
zynq-uboot> mii w 7 9 3b00h
After the execution is completed, the display on the oscilloscope is consistent with the template.
Test mode 2 main mode jitter
zynq-uboot> mii w 7 0 8100h
zynq-uboot> mii w 7 0 0140h
zynq-uboot> mii w 7 9 5b00h
Test mode 3 slave mode jitter
zynq-uboot> mii w 7 0 8100h
zynq-uboot> mii w 7 0 0140h
zynq-uboot> mii w 7 9 7b00h
Test mode 4 waveform distortion test, return loss test, common mode output voltage test
zynq-uboot> mii w 7 0 8100h
zynq-uboot> mii w 7 0 0140h
zynq-uboot> mii w 7 9 9b00h