Part 4: Brief introduction to SOC of zc706
Purpose: Based on the perceptual basic understanding of the above articles, to deeply explore the composition of the SOC chip of the zc706, and give a brief introduction to the SOC.
1 Overview
The core of the Zc706 evaluation board is the Zynq-7000 XC7Z045-2FFG900C AP SoC. This XC7Z045 AP SoC consists of an integrated PS and programmable PL. The high-level block diagram is shown in Figure 1-1.
Figure 1-1 High-level block diagram
As shown in Figure 1-1, PS is mainly composed of APU processor, Interconnect interconnection, internal and external memory interface, and IOP. The PS operates independently of the PL and starts on power-up or restart.
For now we only focus on the part with PS, so the communication interface for the PL part and how to interact with the PL will not be covered.
See Figure 1-2 for a more detailed system-level block diagram:
Figure 1-2 Zynq-7000 block diagram
Select the zc706 development board under vivado, and after importing the zynq7 chip, double-click to open the chip, and you will see the overall SOC composition diagram:
It can be seen that the SOC consists of PS and PL. Xilinx provides a large number of IP cores for the zynq7000 series, and both bare metal and Linux drivers are available for peripherals under PS and PL. (Note that the driver here refers to the driver that operates the underlying hardware status has been provided, but how to configure/operate the peripheral to actually send and receive data needs to be developed by yourself. Although the sample program is provided in the SDK, it does not cover all use cases. .)
The green part in the above figure can be configured, and the gray part cannot be configured.
For the arm program of the general development board, that is, when using the common peripherals on the PS side, namely usb and uart, it can be seen from the above two figures that the transceiver and the memory are exchanged through the Interconnect, and the IRQ interrupt of the peripheral is connected to the APU's GIC (General Interrupt Controller).
Note: For more detailed SOC device information, see the DS190 and UG85 documents.
Note: For more detailed SOC device information, see the DS190 and UG85 documents.
Note: For more detailed SOC device information, see the DS190 and UG85 documents.