1, the onboard clock configuration.
There ZC706 200MHz LVDS differential clock source SiT9102, ZYNQ as a system reference clock.
2, the reset.
Lower right corner of the board is located in front of the user key (SW7, SW8 and SW9 is) as given by the user to reset the FPGA logic.
3, debug interface.
When Vivado debugging environment, the need for Open Target, Connect HW Server and other operations in the Hardware Manager inside.
First set up JTAG BOOT mode on the board, and then connect the device in Hardware Manager. This step can often require reset button SW2 and SW3 for reset operation ZYNQ PS, is not connected to the board in Vivado PS (D21 or B19 pin pulled low, respectively corresponding to the board PS_POR_B SW2 and SW3 and the PS_SRST_B) to try to reconnect.