GPIO, IIC, SPI, URAT

1. GPIO - General-purpose input/output

General-purpose IO, the function is as its name suggests, the pin can be used for its own control, such as clk, generator, chip select, etc. And there must be a register to select these functions: for input, the pin potential can be determined by reading a
register High and low;
for output, you can definitely make this pin output high and low points by writing to a register;
for other functions, it will be controlled by another register

operate

The library function for GPIO operation that can be seen now is V1.8.0, which can be downloaded from the STM official library support. The summary of the document shows that its function is to manage the peripheral functions of GPIO. There are three points in total:

Initialization; 2. Reading and writing; 3. Reuse.
The entire file includes 14 functions: 4 for initialization and configuration; 9 for read and write operations; 1 for reuse.

initialization function
GPIO_DeInit()	Cancels initialization and returns to its default reset value. Default pins are left floating (except JTAG)
GPIO_Init()	Customize the initialization pin according to the initialization structure
GPIO_StructInit()	Initialize pins according to default mode
GPIO_PinLockConfig()	Lock registers GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH can be unlocked using reset operation

Read and write functions
GPIO_ReadInputDataBit() / GPIO_ReadInputData()	Get the pin level configured in input mode
GPIO_ReadOnputDataBit() / GPIO_ReadOnputData()	Get the pin level configured in output mode
GPIO_SetBits()/ GPIO_ResetBits()	Set/reset pin levels used in output mode
GPIO_Write() / GPIO_WriteBit()	Write data to the specified GPIO data port
GPIO_ToggleBits()	Switch the pin level used by the specified GPIO pin, that is, 1 changes to 0, and 0 changes to 1

Reuse function
GPIO_PinAFConfig()	Provide multiplexed functions for a single pin

reference

2. IIC - Inter-Integrated Circuit

The full name is I2C Bus, aka. The integrated circuit bus
I2C is a simple, bidirectional two-wire synchronous serial bus . It only requires two wires to transmit information between devices connected to the bus. That is

SDA: serial data line;
SCL: serial clock line, both are bidirectional I/O lines.

data transmission

1. Data frame format

Each byte sent to the SDA line must be 8 bits, and the number of bytes that can be sent per transmission is not limited; each byte must be followed by a response bit (A=0 indicates response), that is, a total of 9 bits in one frame
The data signals transmitted on the I2C bus are generalized, including address signals and real data signals.
After the host initiates communication, the first byte is the SLAVE address (7bits + R/W addressing signal), 1 means reading. Data Read; 0 means sending data Transmit

a. Master → Slave send Data:
- The shaded area indicates that the data is transmitted from the master to the slave, and the unshaded area indicates that the data is transmitted from the slave to the master. A responds
b. Master ← Slave read Data

c. Master ↔ Slave Read/Transmit Data
The most significant bit (MSB) of the data is transmitted first
- lsb (the least significant bit, the least significant bit) refers to the 0th bit (the lowest bit) in a binary number. It has a weight of 2^0 and can be used to detect the parity of the number; (in big-endian order , lsb refers to the rightmost bit)
- msb (the maximum significant bit), refers to the n-1 bit in an n-bit binary number, with the highest weight 2^n − 1; (in big-endian order, msb refers to the leftmost bit)
If the slave needs to complete some other function (such as an internal interrupt service routine) before it can receive or send the next complete data byte, the clock line SCL can be kept low, forcing the master to enter a wait state when the slave is ready. Data transfer continues after receiving the next data byte and releasing the clock line SCL.

2. Answer response

1. Validity regulations of data bits

Each bit of data transmitted on the I2C bus corresponds to a clock pulse (or synchronous control) , that is, with the cooperation of the SCL serial clock, each bit of data is serially transmitted bit by bit on the SDA.
When the I2C bus transmits data, the data on the data line must remain stable during the period when the clock signal is high level ; only when the signal on the clock line is low level, the high level or low level state on the data line can allow changes
When SCL is at high level, if SDA is at low level; transmit data 0, SDA is at high level: transmit data 1

2. Start and stop signals p

When the SCL line is high level, the change of the SDA line from high level to low level represents the start signal S; and the change of the SDA line from low level to high level represents the termination signal P (1 bit) . After the start signal is generated, the bus is in an occupied state; after the stop signal is generated, the bus is in an idle state

3. Reply signal

All data on the I2C bus is transmitted in 8-bit bytes. Each time the transmitter sends a byte, it releases the data line during clock pulse 9, and the receiver feeds back a response signal.
When the response signal is low level, it is specified as a valid response bit (ACK, referred to as response bit ACKNOWLEDGE ), indicating that the receiver has successfully received the byte; when the response signal is high level, it is specified as a non-response bit (NACK), which generally means The receiver did not receive this byte successfully. The requirement for feedback of a valid acknowledge bit ACK is that the receiver pulls the SDA line low during the low level before the 9th clock pulse, and ensures that during the high level of this clock stable low level

4. The IIC communication process is roughly as follows:

First, the main device sends a START signal. This signal is like shouting to all other devices: Please pay attention! Other devices then start listening to the bus in preparation for receiving data. Next, the master device sends a data frame of a 7-bit device address plus one read and write operation. When the device receives the data, it compares the address to see if it is the target device.
If the comparison does not match, the device enters the waiting state and waits for the arrival of the STOP signal; if the comparison matches, the device will send a response signal - ACKNOWLEDGE in response. When the master device receives the response, it starts transmitting or receiving data. The data frame size is 8 bits, followed by a one-bit acknowledgment signal. The master device sends data and the slave device responds; on the contrary, the master device receives data and the master device responds.
When the data transfer is completed, the master device sends a STOP signal to announce to other devices the release of the bus, and the other devices return to the initial state.
If the slave needs to complete some other function (such as an internal interrupt service routine) before it can receive or send the next complete data byte, the clock line SCL can be kept low, forcing the master to enter a wait state when the slave is ready. Data transfer continues after receiving the next data byte and releasing the clock line SCL.
In the following cases, the slave does not respond, that is, the slave's response signal on SDA is set to a high level, and the master generates a termination signal to end the data transfer on the bus.

When the slave machine does not respond to the master addressing signal for some reason (for example, the slave machine is performing real-time processing and cannot receive data on the bus), it must put the response signal on the data line to a high level, and the slave machine must set the response signal on the data line to a high level. The host generates a termination signal to end the data transfer on the bus
If the slave responds to the master, but cannot continue to receive more data after a period of data transmission, the slave can pass a "non-acknowledge" to the first data byte that cannot be received (slave sda is high level) to notify the host, the host should send a termination signal to end the continued transmission of data
When the master receives data, it must send a signal to the slave to end the transfer after receiving the last data byte. This signal is realized by the slave's "non-response" (pulling sda high). The slave then releases the SDA line to allow the master to generate a kill signal

3. Synchronization of clock signals

The clock synchronization signal when transmitting information on the I2C bus is completed by the logical AND of all devices connected to the SCL line. The transition from high level to low level on the SCL line will affect these devices. Once the clock signal of a certain device jumps to low level, the SCL line will remain low level, causing all the signals on the SCL line to remain low. The device begins a low period. At this time, the low-to-high clock transition of devices with short low-level periods cannot affect the state of the SCL line, so these devices will enter a high-level waiting state. When the clock signals of all devices jump to high level, the low level period ends and the SCL line is released back to high level, that is, all devices start their high level period at the same time. Thereafter, the first device to end the high period pulls the SCL line low again. This generates a synchronization clock on the SCL line. It can be seen that the clock low time is determined by the device with the longest clock low period, and the clock high time is determined by the device with the shortest clock high period.
　　 Insert image description here

4. I2C sending and receiving data timing diagram

key words:

start signal
response signal

Master Send Data:
Insert image description here
red : Master ctl green: Slave ctl

Master Read Data:
Insert image description here
Refer to
the I2C timing diagram
to understand IIC and SPI

3. SPI - Serial Peripheral Interface

SPI is a 4-wire bus protocol. Because of its powerful hardware, the SPI software is relatively simple. It is a high-speed full-duplex synchronous serial bus that can support simultaneous input and output, using 3 communication buses and 1 chip select line:

SCK: Clock signal line, used for communication synchronization

MOSI: Host sends data

MISO: Host receives data

NSS/CS: Chip select signal line, used to select the slave device for communication

start-stop signal

Insert image description here

The start and stop of the signal are determined by NSS, as shown in 1 and 6 in the figure;

A start signal is generated when the NSS level changes from high to low;

A termination signal is generated when the NSS level changes from low to high;

When the Slave detects that its NSS level is set low, it starts communicating with the Master.

data validity

The MOSI and MISO lines transmit one bit of data in each clock cycle of SCK. Developers can set the MSB or LSB first, but they need to ensure that both communication devices use the same protocol. As you can see from the figure above, triggering and sampling are performed on the rising and falling edges of SCK.
SPI has four operating modes - Mode 0, Mode 1, Mode 2 and Mode 3. The difference between them is to define which edges of the clock pulse toggles the output signal, which edge samples the input signal, and the clock The stable level value of the pulse (that is, whether the clock signal is high or low when it is inactive). Each mode is characterized by a pair of parameters, which are called clock polarity (CPOL) and clock phase (clock phase) CPHA.
[Master and slave devices] must use the same operating parameters - SCLK, CPOL and CPHA to work properly. If there are multiple [slave devices] and they use different working parameters, then the [master device] must reconfigure these parameters between reading and writing different [slave devices]

CPOL CPHA

CPOL: (pole), the idle state level of the clock, that is, there is no data transmission time.
CPOL = 0, the sck clock is low level when idle ; CPOL = 1, the sck clock is high level when idle;

CPHA: (phase), the data sampling time of clock
CPHA= 0, the first edge of the sck clock when not idle is the sampling time ; CPHA= 0, the second edge is the sampling time

This constitutes 4 communication modes as follows:
Insert image description here

SPI API

API library
The libspi-master library provides an interface to mediate access to the SPI master. The resource manager layer registers a device name (usually /dev/spi0). Applications access the SPI master by using the functions declared in <hw/spi-master.h>
官网参考
 參考

# include <hw/spi-master.h>

Commonly used functions:

spi_open()
spi_read()
spi_write()
spi_close()

spi_setcfg()
spi_getdevinfo()
spi_getdrvinfo()
spi_xchange()
spi_cmdread()
spi_dma_xchange()

The difference between IIC and SPI

SPI does not stipulate a maximum transmission rate and no address scheme; SPI does not stipulate a communication response mechanism and does not stipulate flow control rules. In fact, the SPI [master] doesn't even know if the specified [slave] exists. These communication controls must be implemented by themselves outside of the SPI protocol. For example, if you want to use SPI to connect a [command-response control type] decoder chip, you must implement a higher-level communication protocol based on SPI. SPI does not care about the electrical characteristics of the physical interface, such as the standard voltage of the signal. Initially, most SPI applications used intermittent clock pulses and transferred data in bytes, but now there are many variants that implement continuous time pulses and data frames of arbitrary lengths.

SPI is suitable for data stream applications, while IIC is more suitable for multi-master device applications of "byte devices"

IIC is different from SPI's single master device. IIC is a bus for multi-master devices. IIC has no physical chip selection signal line and no arbitration logic circuit . It only uses two signal lines - 'serial data' (SDA) and 'serial clock'. ' (SCL)

SPI protocol 1
SPI protocol 2
SPI protocol 3

4. URAT - Universal Asynchronous Receiver/Transmitter

Universal Asynchronous Receiver and Transmitter , an asynchronous communication protocol

Two wires, full duplex, asynchronous communication, slower speed. That is, one sends data and one receives data, and the level logic is a function of time.

Sending and receiving a bit has a fixed width, that is, it is considered to be 1 bit only when it is equal to this time width .

In order to agree on the time width, the concept of bit rate was born : it means that a 1s signal can transmit N bits of data, and the unit is bps=bit per second. For example, 9600bps = 1s to send or receive 9600 bit data, then the time width of 1bit data is 1/9600 s

Common bit rates - 9600bps 19200bps 38400bps 57600bps 115200bps

The difference between URAT interface and COM port:

The serial port mentioned in embedded generally refers to the UART port, but we often don’t understand the difference between it and the COM port, as well as the relationship between RS232, TTL, etc. In
fact, UART and COM refer to the physical interface form (hardware), while TTL, RS-232 refers to the level standard (electrical signal).
The UART has 4 pins (VCC, GND, RX, TX) and uses TTL level. The low level is 0 (0V) and the high level is 1 (3.3 V or above)
VCC: power supply pin, usually 3.3v. There is no overcurrent protection on our board. It is generally safer not to connect this pin.
GND: Ground pin. Sometimes there is a problem with rx receiving data, so you need to connect this pin, generally it is not necessary to connect
RX: receive data pin
TX: send data pin

The COM port is a commonly used port on our desktop computers (picture below), with 9 pins. The RS232 level is used, which is a negative logic level. It defines +5 +12V as low level, _{and -12} -5V as high level. level