Vivado IP core provides a powerful FIFO generator that can quickly generate FIFO IP core through graphical configuration.
This article will introduce in detail how to configure a FIFO IP core in Vivado and how to call this FIFO IP core.
1. Configuration of FIFO IP core
1. Create a new FIFO IP
Find the FIFO Generator IP core in Vivado's IP Catalog and double-click to open the parameter configuration interface.
2. Configure basic parameters of FIFO
(1) Interface type
Native interface FIFOs：
This is the most basic FIFO interface, including data input, output port, write enable, read enable and other signals.
AXI Memory Mapped interface FIFOs：
This interface encapsulates the FIFO into an AXI memory-mapped IP core that can be accessed through the AXI bus.
AXI4-Stream interface FIFOs：
This interface is compatible with the AXI4-Stream protocol and is suitable for use in streaming data transmission scenarios.
(2) Clock type and resource type
Clock: synchronous clock (common clock) and asynchronous clock (Independent clock)
资源：block RAM、Distributed RAM、Shift Register、Built-in FIFO
3. Configure fifo interface parameters
(1) Read mode setting
Standard FIFO: Standard read mode, output data in the next cycle after receiving read enable
First Word Fall Through: First in, first out mode. As long as there is data in the FIFO, the first data will be automatically output and this data output will be maintained.
(2) Data interface parameter setting
The bit width and depth of the FIFO read data interface, the bit width and depth of the FIFO write data interface
(3) ECC and output register settings
(4) Initialization settings
4. Status signal interface settings
According to actual needs, just select the corresponding status signal.
Note (Programmable Flags): Customize the signal of whether the FIFO buffer depth reaches the set value. It can be used to set the half-full or half-empty signal.
5. Counting port settings
Fifo cached data depth count, optional.
6. Overview of FIFO setting parameters
This is an overview of the setting parameters of the FIFO IP. You can see resource consumption, width, depth, read latency and other information.
7. Click OK to generate the FIFO IP core.
2. Interface of FIFO IP core
The generated FIFO IP core provides the following interfaces:
wr_clk write clock
rd_clk read clock
din data input port, the width is the configured Data Width;
wr_en write enable signal;
rd_en read enable signal;
dout data output port;
full full flag, high level indicates that the FIFO is full;
empty empty flag, high level indicates that the FIFO is empty;
almost_full almost full flag;
almost_empty almost empty flag;
valid valid data flag
rd_data_count read count
wr_data_count write count
overflow writes overflow mark
underflow reads overflow mark
3. Calling of FIFO IP core
The call of the FIFO IP core is very simple. You only need to connect the interface appropriately and control the read and write enable signals according to the Full and Empty flags. A simple calling example is given below:
module fifo_test(
input clk,
input [17:0] din,
input wr_en, rd_en,
output valid,
output [17:0] dout,
output full, empty, overflow, underflow
);
fifo_generator_0 fifo_inst(
.clk(clk),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout),
.full(full),
.empty(empty),
.overflow(overflow),
.valid(valid),
.underflow(underflow)
);
endmodule
In this example, din and wr_en are connected to the input ports of the FIFO, and dout and empty are connected to the output ports. The full signal needs to be checked when writing data, and the empty signal needs to be checked when reading data to avoid overflow and underflow.
The following is a simple testbench of the FIFO IP core:
`timescale 1ns / 1ps
module fifo_testbench();
reg clk;
reg [17:0] din;
reg wr_en;
reg rd_en;
wire valid;
wire [17:0] dout;
wire full, empty, overflow, underflow;
fifo_test dut(
.clk(clk),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.dout(dout),
.full(full),
.empty(empty),
.overflow(overflow),
.valid(valid),
.underflow(underflow)
);
always #5 clk = ~clk;
initial begin
clk = 0;
wr_en = 0; rd_en = 0;
#10;
wr_en = 1; din = 18'd1;
#10;
wr_en = 1; din = 18'd2;
#10;
wr_en = 1; din = 18'd3;
#10;
wr_en = 0; rd_en = 1;
#10;
wr_en = 0; rd_en = 1;
#10;
wr_en = 1; din = 18'd4;
wr_en = 1; din = 18'd5;
#10;
wr_en = 0; rd_en = 1;
#10
wr_en = 0; rd_en = 1;
#10;
$finish;
end
endmodule
This testbench tests the writing and reading functions of the FIFO by applying different read and write enable signals.
Simulation test chart:
(1) FIFO read mode is set to "Standard FIFO"
The valid signal is completely controlled by rd_en.
(2) The FIFO read mode is set to "First Word Fall Through"
After caching a certain length of data, the first data is automatically read and held until the next rd_en signal arrives.
4. Summary
Through the above description, we have introduced in detail how to configure the FIFO IP core in Vivado, the interface signal of FIFO, and a simple example of how to call the FIFO IP core. FIFO is a very commonly used IP core. Vivado's FIFO Generator can greatly simplify the process of configuring and using FIFO.
xilinx official manual:
AMD Adaptive Computing Documentation Portal
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