Two IPs that are very frequently used in FPGA development are FIFO and BRAM. The Vivado FIFO IP has been introduced in detail in the previous article. Today we will talk about the BRAM IP.
This article will introduce in detail how to configure and use BRAM IP in Vivado.
1. Configuration of BRAM IP core
1. Open the BRAM IP core
Find the Block Memory Generator IP core in Vivado's IP Catalog, and double-click to open the parameter configuration interface.
2. Configure the basic parameters of BRAM IP
(1) IP name
The name of the customized IP can only be set at the time of customization, and cannot be modified later.
The IP name setting is simple and easy to understand. You can set it according to the function or data width and depth. For example, BRAM_8x256 means that the data width is 8bit and the data depth is 256bit.
(2) Interface Type
Native: The most basic interface, including data writing, data reading and other signals.
AXI4: AXI4 bus communication protocol interface
(3) Storage type (Memory Type)
Single Port RAM: Single port RAM
Simple Dual Port RAM: Simple dual-port RAM, optional synchronous clock and asynchronous clock. Port A only supports writing data, and port B only supports reading data.
True Dual Port RAM: True dual-port RAM, optional synchronous clock and asynchronous clock, both A port and B port support writing data and reading data.
Single Port ROM: Single port ROM
Dual Port ROM: Dual port ROM, both A port and B port can read data
3. Configure A port or B port parameters
The parameter configuration interfaces of port A and port B are basically the same. Only the parameter configuration of port A is introduced here.
(1) Storage size setting (Memory Size)
Set the data bit width and depth of the read data or write data end. The data bit width range is 1~4608bit, and the data storage depth is 2~1048576.
Operating mode: When reading and writing the same address, the operating mode settings are: write priority, read priority, unchanged. It is recommended that this situation not occur in actual applications.
Enable Port Type: Set whether to open the port enable control signal.
(2) Output data storage setting
Primitives Output Register: Whether the output data is inserted into a register. If this is not selected, the read data delay is only 1 cycle, otherwise the read data delay is 2 cycles.
It is recommended to select this output register to improve timing.
(3) Reset parameter settings
RSTA Pin (setreset pin): Reset port selection, if selected, the reset port is opened.
Output Reset Value (Hex): Set the output data value after the reset takes effect, the default is 0
4、Other Options
This part of the initialization value may not be of much use to RAM, but it is very important to ROM.
Select this Load Init File, then click "Browse" to select the "coe or mif" format file, and finally click "Edit" and select "Valide" in the opened interface to verify it. If there is a problem, this part will prompt red text. Otherwise, just continue to the next step.
5. Overview of IP setting parameters
Overview of IP setting parameters, including resource consumption, width, depth, read latency and other information.
6. Click OK to generate the IP core.
After the IP core generation is completed, click "IP source" under the source window, left-click the IP, and under "Instantiation Template", double-click the "veo" suffix file to see the instantiation template.
2. Interface of BRAM IP core
1. Clock signal and reset signal
Synchronous clock clk, reset signal rst
Asynchronous clock clka (A port clock) clkb (B port clock), reset signal rsta (A port reset), rstb (B port reset)
2. Port signal
The signals of ports A and B are basically the same. Here we take port A as an example.
ena A port enable signal
wea A port write enable signal
addra A port read and write address
Write data to dina A port
Read data from douta A port
3. Calling of BRAM IP core
The call of the BRAM IP core is very simple. Here is a simple dual-port RAM under synchronous clock as an example:
module top (
input clk,
input [7:0] data_in,
input wr_en,
input [7:0] wr_addr,
input [7:0] rd_addr,
output [7:0] data_out
);
BRAM_8x256 u_BRAM_8x256 (
.clka(clk), // input wire clka
.ena(1'b1), // input wire ena
.wea(wr_en), // input wire [0 : 0] wea
.addra(wr_addr), // input wire [7 : 0] addra
.dina(data_in), // input wire [7 : 0] dina
.clkb(clk), // input wire clkb
.enb(1'b1), // input wire enb
.addrb(rd_addr), // input wire [7 : 0] addrb
.doutb(data_out) // output wire [7 : 0] doutb
);
endmoduleThe following is a simple testbench of the BRAM IP core:
module test;
reg clk;
reg [7:0] din;
reg wen;
reg [7:0] waddr;
reg [7:0] raddr;
wire [7:0] dout;
top u_top(
.clk(clk),
.data_in(din),
.wr_en(wen),
.wr_addr(waddr),
.rd_addr(raddr),
.data_out(dout)
);
initial begin
clk = 0;
wen = 0; waddr = 0; raddr = 0;
#10 wen = 1; waddr = 1; din = 5;
#10 wen = 1; waddr = 2; din = 6;
#10 wen = 1; waddr = 3; din = 7;
#10 wen = 1; waddr = 4; din = 8;
#10 wen = 1; waddr = 5; din = 9;
#10 wen = 0; raddr = 1;
#10 wen = 0; raddr = 2;
#10 wen = 0; raddr = 3;
#10 wen = 0; raddr = 4;
#10 wen = 0; raddr = 5;
#30 $finish;
end
always #5 clk = ~clk;
endmoduleSimulation test chart:
References: xilinx official manual or network disk download
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