FMQL development process
The overall development process is as follows:
Specific development process:
- Vivado project construction
- First, according to the functional requirements of your own project, combined with the schematic diagram, clarify the resources of the PS and PL parts that need to be built in the vivado project .
The build uses the vivado version of vivado2018.2
- Create a vivado project:
Double-click the vivado software, open it and click the Create Progect option
Click next, enter the project name, select the save path, and check Create Project Subdirector. The path cannot have Chinese characters, and the project name cannot have a "-" middle line.
Continue to click next, select the first option RTL Project, and check Do not specify sources at this time. This option is to add programming files. We generally do not need to write code ourselves when developing zynq, so check this option.
Click next, and the window for selecting the SOC model will pop up. The chip model can be obtained from the schematic diagram. If the chip model in the schematic diagram is not complete, you can go to the hardware and ask for the specific model. Search for the chip model you need in the search, and select the chip. model, click next
After that, a parameter display interface will pop up. After confirming that the SOC model is correct, click finish to complete the creation of the project.
After the project is created, it will enter the formal editing project interface, as shown below
Click the Create Block Design option in the left menu bar, a pop-up window, fill in the name of the block design project, the default name is used here, you can modify it according to your needs
Click OK, then click the Create Block Design option on the left menu, as shown below, you can turn off
The two windows of IP Catalog and Project Summary are generally not used.
Click "+" on the right page or in the menu bar above the right page to add an IP core, or right-click the blank part on the right, and select the Add IP option in the pop-up menu. The first thing you must add is the PS IP of zynq Core, click the plus sign and search for zynq to find out the IP core of PS, select and double-click to add.
You can double-click the PS IP core to open the PS configuration interface, configure PS resources, etc. The most important thing to configure is the selection of DDR. Similarly, you can also double-click the IP of the PL part to open the configuration interface to configure some parameters.
Other specific details of building block design will not be repeated here, and the project connection is as follows:
https://download.csdn.net/download/qq_38584212/87924602
After building the project, you must first save it, and then click the check button in the menu on the upper right (marked in red in the figure) to check whether the built block design is correct, and the successful pop-up means that the block design has no connection errors.
Right-click design_1 with a yellow triangle in the Source menu, and select Generate Output Products from the pop-up menu
Select the Global option in the pop-up window, click Generate, and output the product.
Afterwards, right-click the design_1 with the small yellow triangle, and select Create HDL Wrapper in the pop-up menu to generate the top-level file. The top-level file is used for subsequent addition of constraint files to generate corresponding pins that need to be constrained.
Double-click the design1_wrapper with a blue dot in front of the Source menu, and you can see some pins that have been generated that need to be constrained in the right window.
Next, you need to add corresponding constraints to these pins, right-click on constrs_1 in the Source menu, and select Edit Constraints Sets from the pop-up menu
Click Create File in the newly popped-up window, fill in the name of the constraint file .xdc, click OK, and a new constraint file with the suffix .xdc will be added in the constrs_1 directory.
Then click the Open Elaborated Design option in the left menu, and the interface for adding constraints will pop up (depending on the size of the block design, the opening time is different, and some projects may take ten or twenty minutes to open). After opening, it is shown in the figure below Indicates that you need to select the corresponding constraint pin and voltage until there is no red word prompt in the table, indicating that all the pins that need to be added are assigned corresponding constraints.
You can also choose to add constraints by manually adding code in the previously created xdc file (this method is not recommended, it is error-prone)
The constraint pins of the PL terminal required in your own project should be found in the schematic diagram.
For example, the constraint of the network port can be searched from the bit number of the RJ45 socket, and then find the corresponding PYH chip. The connection of the PHY chip is the constraint of the PL terminal.
After adding constraints, save the project, and the word Reload will be prompted on the top. Click Reload, and the corresponding .xdc file will automatically add the constraint code.
Once all done, click on the Generate Bitstream option in the left menu
In the pop-up interface, select the first option, and then pull down to select the number of CPUs used to compile the project. The more the number, the faster the project will be compiled, but the more computer resources will be occupied. Click OK and wait for the completion of synthesis, implementation, and generation. bit file.
After the bit file is successfully generated, the following window will pop up, click Cancel
To export the hdf file, click File-Export-Export HardWare
In the pop-up window, check include bitstream, click ok, and there will be an additional .sdk folder in the corresponding vivado project directory, which stores .hdf files.
The next step is to go to the directory of the vivado project and find the four files .bit, .hdf, .bd, and .xci required for FMQL transplantation. The directories where the four files are located are as follows:
.bit file
路径：\your_project\project_1.runs\impl_2\*.bit
.hdf file
Path: \your_project\project_1.sdk\*.hdf
.bd file
路径：\your_project\project_1.srcs\sources_1\bd\design_1\*.bd
.xci file
路径:\your_project\project_1.srcs\sources_1\bd\design_1\ip\
design_1_processing_system7_0_1\*.xci
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- FMQL porting part
Open the Procise software, create a new Procise project, click New Project, fill in the project name, and click Next
To choose the chip model, you can directly look at the model printed on the chip, or look at the schematic diagram and ask your hardware colleagues. If you choose the wrong chip model, the final system may fail to start or freeze.
After that, keep clicking Next and click fimish to complete the new project
Click Tools-Integrated Tools Options in the upper menu bar
In the pop-up window, add the IAR installation path to the IAR option, so that the IAR software can be opened directly and automatically through Procise.
Click PSOC in the top menu bar, select the first item From Vivado in the drop-down menu
Click Browse in the pop-up window, the first option selects the .bd file among the four files taken out from the vivado project before, the second option selects the .xci file, and then click OK.
After clicking OK, a dialog box will pop up, prompting to lead out DDR and FIXED_IO, click OK
Wait for a few seconds, a new window pops up, select the two options FSBL and DeviceTree, and click OK
Wait for a few seconds and Procise will automatically connect to open the IAR software, click the make button in the upper menu of the IAR software, circled in red in the figure, and the compilation window below will prompt errors: 0, indicating that the compilation is successful.
Remind again: IAR software cannot be used remotely, otherwise compilation will fail
After the compilation is successful, fsbl and device tree source code folders will be generated in the Procise project directory
Fsbl路径：\Your Project\SDK\design_1_platform\FSBL\Debug\Exe\fsbl.out
DeviceTree路径：\ Your Project \SDK\design_1_platform\DeviceTree
Take out the fsbl.out file and the DeviceTree folder
Three files fsbl.out, bit file, and uboot.elf are used to generate BOOT.bin
The DeviceTree folder and the .hdf file are used to compile and generate the .dtb device tree file
Switch back to the Procise software again, select the PSOC-Create Boot Image option in the menu bar
Select Basic in the pop-up window, click Browse on the first line, and select the path to store the generated BOOT.bin and .bif files.
Lock in pull down to select the storage path of the BOOT.bin file, and fill in the name of the .bif file for File name. We don’t need this file, so just fill it in as you like, and then click save.
Click the Add button, click the Browse button in the pop-up window, and select to add fsbl, bit files, and u-boot.elf files in turn. The order of adding must not be wrong, otherwise Linux will not start.
After all are added, finally click Create Image to generate the BOOT.bin file.
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- Compile and generate the .dtb device tree file in the virtual machine
Open the virtual machine used to compile the FMQL device tree
Copy the DeviceTree folder in the Procise project directory generated by the previous IAR compilation to any directory of the virtual machine (this directory is defined by yourself, and then modify the path of DeviceTree to the path defined by yourself in the command to compile the device tree)
I put it in a directory defined by myself.
Then copy the .hdf file to the following directory of the virtual machine:
Return to the compilation environment directory FMQL-Linux-SDK_20201022:
Right-click the mouse and select Open in Terminal
Execution command: source env.sh The reopened console needs to re-execute the command
Execution command: ./build.sh --hw /home/fmsh/tangbojian/DeviceTree/ --hdf device-tree/xlnx-dts/design_1_wrapper.hdf dtb
Compile the device tree
Among them, the /home/fmsh/tangbojian/DeviceTree/ path is configured as the path where the DeviceTree folder is stored, and design_1_wrapper.hdf is changed to the name of the .hdf file generated in the viaodo project.
If the built vivado project does not have a PL part, it is not necessary to import the .hdf file when compiling the device tree, and the command to compile the device tree executed becomes:
./build.sh --hw /home/{user_name}/Downloads/DeviceTree/ --nofpga dtb
After the device tree is successfully compiled, the system-top.dtb file will be generated in the Image directory, and it needs to be renamed to devicetree.dtb for use.
Modify the device tree node:
fmql and zynq have different methods of modifying device tree nodes. The nodes added by fmql are placed in a file named system-user.dtsi, and new child nodes need to be defined through the reference of the parent node. The corresponding directory is as follows:
Do not modify the device tree in the other four files. Even if it is modified, it will not take effect after compilation. The remaining four files are generated after compiling through the DeviceTree folder and the .hdf file, which contains the resource device tree built by the vivado project. The description of the node, when you use it, you can compile it once without modifying the system-user.dtsi file, so that the device tree nodes in the other four files will be updated according to your DeviceTree folder and . The reference names of the device tree nodes in the four files, and add new device tree child node information by reference in the system-user.dtsi file.
The following is an example of adding the system-user.dtsi file of the EMMC partition node and the PYH node in the network port:
The newly added device tree node information, after recompilation, cannot be seen in the above four files. Only by decompiling the system-top.dtb file just compiled can you see whether the newly added nodes are valid.
Decompile command: dtc -I dtb -O dts system-top.dtb > devicetree.dts
The compiled devicetree.dts file can be opened and viewed directly.
The address information of the PHY node is determined according to the schematic diagram and the manual of the PHY chip.
Plus Rootfs can start the system.
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