(1) Detailed explanation of MII/MDIO interface
This article mainly analyzes the signal definition of MII/RMII/SMII, and GMII/RGMII/SGMII interface, and related knowledge. At the same time, this article also summarizes the RJ-45 interface, and analyzes the design in 10/100 mode and 1000M mode method.
The MII interface provides the interconnection technology between MAC and PHY, and between PHY and STA (Station Management). This interface supports data transmission rates of 10Mb/s and 100Mb/s, and the bit width of data transmission is 4 bits. When it comes to MII, terms such as RS, PLS, and STA may be involved. Let's talk about the corresponding relationship between them. The so-called RS is the Reconciliation sublayer, and its main function is to provide a signal mapping mechanism between MII and MAC/PLS. The relationship between them (RS and MII) is as follows:
The Management Interface of the MII interface can control multiple PHYs at the same time. The 802.3 protocol supports up to 32 PHYs, but there are certain restrictions: it must meet the connector characteristics required by the protocol. The so-called Management Interface, namely MDC signal and MDIO signal.
The relationship between RS and PLS has been mentioned before, and the objects connected by the MII interface. They are connected through the MII interface, the schematic diagram is as follows. It can be seen from the figure that the Management Interface of MII is connected with STA (Station Management).
The interface supports 10Mb/s and 100Mb/s, and all functions and timing relationships are consistent in the two working modes, the only difference is the frequency of the clock. 802.3 requires that the PHY does not necessarily have to support these two rates, but it must be described and fed back to the MAC through the Management Interface.
The signal definition and timing characteristics of the MII interface will be introduced in detail below. Since the MII interface has MAC and PHY modes, it will be analyzed according to these two different modes, and RMII/SMII will also be introduced.
The MII interface can be divided into MAC mode and PHY mode. Generally speaking, MAC and PHY are connected, but MAC and MAC can also be connected.
The previous 10M MAC layer chip and the physical layer chip transmit data through a data line, and the clock is 10M. In 100M, if a data line is also used to transmit data, the clock needs to be 100M. It will bring some problems, so the MII interface is defined, which uses 4 data lines to transmit data, so that when transmitting 100M data, the clock will be reduced from 100M to 25M, and when transmitting 10M data, the clock will be reduced To 2.5M, thus realizing the compatibility of 10M and 100M.
The MII interface mainly includes four parts. One is the interface for sending data from the MAC layer to the physical layer, the other is the interface for receiving data from the physical layer to the MAC layer, the third is the status indication signal from the physical layer to the MAC layer, and the fourth is the transmission control between the MAC layer and the physical layer and MDIO interface for status information.
The MAC mode definition of the MII interface:
MII interface PHY mode definition:
In the MII interface, the TX channel reference clock is TX_CLK, the RX channel reference clock is RX_CLK, and 802.3-2005 defines the relationship between them.
As can be seen from Figure 3, that is, The clock to output delay shall be a min of 0 ns and a max of 25 nsSpec only defines the transmission characteristics of the MAC side of the TX channel, and the receiving characteristics of the PHY side of the TX channel Properties are not defined. IC Vendor can make appropriate adjustments to the receiving characteristics of the PHY on the side of the TX channel, as long as the final timing meets the sending characteristics of the MAC side on the TX channel.
It can be seen from Figure 4 that The input setup time shall be a minimum of 10 ns and the input hold time shall be a minimum of 10 ns. Spec only defines the receiving characteristics of the MAC side on the RX channel, while the RX channel PHY The transmission characteristics of one side are not defined. IC Vendor can properly adjust the sending characteristics of the PHY on the side of the RX channel, as long as the final timing meets the receiving characteristics of the MAC side on the RX channel.
<1>: TX_CLK (transmit clock), TX_CLK (Transmit Clock) is a continuous clock signal (that is, the signal is always present when the system starts), it is TX_EN, TXD, and TX_ER (the signal direction is from RS to PHY) The reference clock, TX_CLK is driven by the PHY. The clock frequency of TX_CLK is 25% of the data transmission rate, and the deviation is +-100ppm. For example, in 100Mb/s mode, the TX_CLK clock frequency is 25MHz, and the duty cycle is between 35% and 65%.
<2>: For the same RX_CLK , it has the same requirements as TX_CLK, the difference is that it is the reference clock for RX_DV, RXD, and RX_ER (signal direction is from PHY to RS). RX_CLK is also driven by the PHY. The PHY may extract the clock RX_CLK from the received data, or it may drive RX_CLK from a nominal reference clock (eg, the TX_CLK reference)
<3>: TXD (transmit data), TXD is driven by RS, synchronized with TX_CLK, within the clock cycle of TX_CLK, and TX_EN is valid, the data on TXD is received by PHY, otherwise the data of TXD has no effect on PHY.
<4>: TX_ER (transmit coding error), TX_ER is synchronized with TX_CLK. During data transmission, if TX_ER is valid for more than one clock cycle, and TX_ENTX_ER is valid at this time, it does not affect the PHY working at 10Mb/s or when TX_EN is invalid. data transmission. In the connection of the MII interface, if the TX_ER signal line is not used, it must be pulled down to ground.
<5>: RX_DV (Receive Data Valid), RXD_DV is synchronized with RX_CLK, driven by PHY, its function is the same as TX_EN in the transmission channel, the difference is a little difference in timing: in order for the data to be successfully received by RS , the valid time of RXD_DV must cover the entire FRAME process, that is, starting no later than the Start Frame Delimiter (SFD) and excluding any End-of-Frame delimiter, as shown in Figure 7 below.
<6>: RXD (receive data), RXD is driven by RS, synchronized with RX_CLK, within the clock cycle of RX_CLK, and RX_DV is valid, the data on RXD is received by RS, otherwise the data of RXD has no effect on RS. While RX_DV is de-asserted, the PHY may provide a False Carrier indication by asserting the RX_ER signal while driving the value <1110> onto RXD<3:0>.
<7>: RX_ER (receive error), RX_ER is synchronized with RX_CLK, its role in the RX channel is similar to the impact of TX_ER on the data transmission of the TX channel.
<8>: CRS (carrier sense), CRS does not need to be synchronized with the reference clock, as long as there is a sending or receiving process on the channel, CRS needs to be valid. The behavior of the CRS signal is unspecified when the duplex mode bit 0.8 in the control register is set to a logic one (auto-negotiation disabled, manually set to full-duplex mode), or when the Auto-Negotiation process selects a full duplex mode of operation, that is, the half-duplex mode signal is valid, and the full-duplex mode signal is invalid.
<9>: COL (collision detected), COL does not need to be synchronized with the reference clock. The behavior of the COL signal is unspecified when the duplex mode bit 0.8 in the control register is set to a logic one (auto-negotiation disabled, manually set to full-duplex mode), or when the Auto-Negotiation process selects a full duplex mode of operation. That is, the half-duplex mode signal is valid, and the full-duplex mode signal is invalid.
The MDIO interface includes two signal lines: MDC and MDIO, through which the MAC layer chip (or other control chip) can access the registers of the physical layer chip (the register set introduced in the previous 100M physical layer chip, but not limited to 100M physical layer chip , 10M physical layer chip can also have these registers), and control and manage the physical layer chip through these registers. The MDIO management interface is as follows:
MDC: The clock of the management interface, which is a non-periodic signal, the minimum period of the signal (actually the sum of positive level time and negative level time) is 400ns, the minimum positive level time and negative level time are 160ns, and the maximum positive and negative Level time is unlimited. It has nothing to do with TX_CLK and RX_CLK.
MDIO is a bidirectional data line. It is used to transmit the control information of the MAC layer and the state information of the physical layer. MDIO data is synchronized with the MDC clock and is valid on the rising edge of MDC. The data frame structure of the MDIO management interface is as follows:
PRE: Frame prefix field, which is 32 consecutive "1" bits. This frame prefix field is not necessary, and some physical layer chips do not have this field for MDIO operations.
OP: frame operation code, bit "10" indicates that the frame is a read operation frame, and bit "01" indicates that the frame is a write operation frame.
PHYAD: The address of the physical layer chip, 5 bits. Each chip compares its own address with these 5 bits. If it matches, it responds to the following operations. If it does not match, it ignores the following operations.
REGAD: used to select the address of one of the 32 registers of the physical layer chip.
TA: state transition domain, if it is a read operation, MDIO is in a high-impedance state at the first bit, and the physical layer chip sets MDIO to "0" at the second bit. If it is a write operation, the MDIO is still controlled by the MAC layer chip, which continuously outputs two bits of "10".
DATA: The data field of the register of the frame, 16 bits, if it is a read operation, it is the data sent by the physical layer to the MAC layer, and if it is a write operation, it is the data sent by the MAC layer to the physical layer.
IDLE: The idle state after the end of the frame. At this time, MDIO is driven passively and is in a high-impedance state, but generally a pull-up resistor is used to make it at a high level, that is, the MDIO pin needs a pull-up resistor.
The timing relationship of the MDIO data frame is as follows:
The MII interface also has some shortcomings, mainly because it has a lot of interface signal lines. There are 14 data lines in the sending, receiving and indicating interfaces (excluding the signal lines of the MDIO interface, because they are shared by all MII interfaces). When the port data is large, it will cause the problem of a large number of pins of the chip, which brings certain problems to the design of the chip and the design of the single board. In order to solve these problems, people have designed two new MII interfaces, which are RMII interface (Reduced MII interface) and SMII interface (StreamMII interface).
Both of these two interfaces reduce the data lines of the MII interface, but they are generally only used in switching MAC chips and multi-port physical layer chips of Ethernet switches, and are rarely used in single-port MAC layer chips and physical layer chips. Both RMII interface and SMII interface can be used for 10M Ethernet and 100M Ethernet, but it is impossible to be used for 1000M Ethernet, because the clock frequency is too high at this time, which is impossible to realize.
The picture below is from the datasheet of DM368:
【From】http://dpinglee.blog.163.com/blog/static/144097753201041131115262/