1 Introduction
After the entire uvm study is completed, a preliminary understanding and a simple verification environment are built, so a verification environment is built for a uart module; the specific implementation and detailed introduction of the uart can be found in this article: UART project verification (2) spec reading
The architecture block diagram of the entire verification process is as follows, and the subsequent verification environment will be built based on this diagram:
For verifying an IP, it is first necessary to specify the verification strategy and extract the verification points, and make the corresponding test plan, so it is specified as follows: UART project verification (3) Verification strategy and verification point extraction
2. Overall environment construction
The entire verification environment consists of three parts. We use two integrated uvcs, namely apb_uvc and uart_uvc. These two parts are already integrated, and they can be directly integrated into our verification environment. Another part of the principal verification environment uart_ctrl is the environment we need to configure.
The apb_uvc part includes (the code will not be posted one by one):
The uart_uvc part includes (the code will not be posted one by one):
The uart_ctrl part builds the most basic part of the entire verification architecture, including two paths from apb to send data to dut to receive data and dut to send data, and uart_uvc to receive data; to build the environment, we first build the path from apb to send data to dut to receive data Verify the environment, the correct construction of this part is the basis for the subsequent addition of uart_uvc.
1.1 sequence_lib
The entire verification environment includes apb_uvc and uart_uvc, in which the basic components have been integrated, and the sequence of two uvcs can be used directly, and a new sequence can be written
1.1.1 uart_ctrl_sequence_lib
The sequence of apb_uvc and uart_uvc is instantiated;
1.1.2 virtual_uart_ctrl_sequence_lib
1.2 virtual_sequencer
Two sequencers of apb_uvc and uart_uvc are instantiated in virtual_sequencer
1.3 uart_ctrl_env
The env instance of apb_uvc and uart_uvc is instantiated and declared in uart_ctrl_env
1.4 top top-level construction
1.4.1 top
I have been reminded that the interrupted connection here may be problematic, but I don't know how to correct it ==
Two interfaces and dut are instantiated in top, and the virtual interface is passed to the env corresponding to the two uvcs by using config_db, and then the case is run to generate a simple reset and clock stimulus.
1.4.2 pkg
The pkg included in top has various public files inside.
1.5 base_test
In base_test, the env, virtual_sequencer, and config in uart_ctrl are created, connected and declared, and the virtual_sequencer in uart_ctrl is connected to the virtual_sequencers of the two uvcs respectively, and the config configuration files corresponding to the two uvcs are passed to the corresponding uvcs.
1.6 Smoke test
So far, the large framework of the entire verification environment has been built, and the rest is to write each of the remaining components, then connect them in the environment, and call them in top.
Do a smoke test to check that the environment is functioning properly
The entire uvm verification environment tree structure is printed successfully, and the basic environment runs successfully
2 Other components and detail filling
2.1 Configuration file config
Configure the working mode and parameters of the two uvcs by setting the parameters in config
2.2 Add sequence for simple verification
Write a sequence in which apb writes 5 pieces of data to dut for environmental verification
2.3 更新virtual_uart_ctrl_sequence_lib
Declare the above sequence in virtual_uart_ctrl_sequence_lib
2.4 Write the corresponding case
3 Simulation waveform
The written apb2dut writes the case of Wubi data successfully written
4 Epilogue
So far, the establishment of the verification environment is over. Through the actual practice of this project, the specific application of uvm methodology has been practiced, and at the same time, a simple verification environment has been built by myself; but there are still some problems, such as the understanding of DUT is not very good, resulting in the waveforms tested I don't know if it is a bug of the DUT or it should be. I will strengthen my understanding of the uart module in the future.
I am just a beginner at the moment, so please criticize and correct me if I am wrong in the article! There are still too many things to learn, but as long as you keep learning, study hard and practice more, I believe you will be able to succeed!
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