When setting up the verification environment, we will sometimes environmental package to package them, when the force signal design code will encounter Hierarchical reference from package these errors, a problem-solving approach is by defining the interface corresponding task is achieved.
the following steps:
1. define the interface corresponding to the interface, the package will need to force the signal into the Task;
2. in the embodiment of the testbench interface, this interface uvm_config_db passed through a corresponding assembly which;
3. component after obtaining the interface, you can call the corresponding position in the task, the assignment to achieve the force signal.
Referring verification environment as follows:
1. Preparation of interface
2. Get interface
3. use
