1.1 about uart
The UART (PL011) is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-Chip (SoC) peripheral. The UART is an AMBA slave module connected to the Advanced Peripheral Bus (APB). The UART includes an Infrared Data Association (IrDA) Serial Infrared (SIR) protocol encoder/decoder (ENDEC).
1.1.1 features
• Programmable FIFO can be disabled to 1 byte depth.
• Programmable baud rate generator. This allows dividing the reference clock by (1x16) to (65535 x16) and generating the internal x16 clock.
• Independent masking of transmit FIFO, receive FIFO, receive timeout, modem status, and error condition interrupts
• Supports direct memory access (DMA).
• Fully Programmable Serial Interface Features:
- Data can be 5, 6, 7 or 8 bits configurable
-Even, odd, stick or no parity bit generation and detection
-1 or 2 stop bit generation
- Baud rate generation, DC up to UARTCLK_max_freq /16
1.1.2 Programmable parameters (programmable parameters)
• Communication baud rate, integer and fractional parts
• Data bits
• Number of stop bits, 1.5 stop bits
• Parity mode
• FIFO enabled (depth 16) or disabled (depth 1)
• FIFO trigger level can be selected among 1 \8, 1 \4, 1 \2, 3 \4 and 7 \8.
• Internal nominal 1.8432MHz clock frequency (1.42–2.12MHz) for generating shorter bit durations in low power mode
• Hardware flow control.
2.1 Function overview (function overview)
UART implementation:
• Serial to parallel conversion of data received from peripherals (rx direction)
• Parallel-to-serial conversion of data transferred to peripherals. (tx direction)
The CPU reads and writes data and control/status information through the AMBA APB interface. The transmit and receive paths are buffered by internal FIFO memory that can independently store up to 16 bytes in transmit and receive modes.
includes a programmable baud rate generator,
• This generator generates a common transmit and receive internal clock from the UART internal reference clock input, UARTCLK
• Provides similar functionality to industry standard 16C550 UART devices
• Supports baud rates up to 460.8Kbits\/s, depending on the UARTCLK reference clock frequency.
UART operation and baud rate values are controlled by the Line Control Register (UARTLCR_UH) and Baud Rate Divisor Registers (UARTIBRD and UARTFBRD).
2.2 Functional frame diagram
• APB interface AMBA: APB interface generates read and write decodes for accessing status\control registers and transmit\receive FIFO memory.
• Register block: The register block stores data written or read through the AMBA APB interface.
• Baud Rate Generator: The Baud Rate Generator contains a free-running counter for generating the internal x16 clock, Baud16 and IrLPBaud16 signals. Baud16 provides timing information for UART transmit and receive control. Baud16 is a pulse stream with a width of one UARTCLK clock cycle and a frequency of 16 times the baud rate. IrLPBaud16 provides timing information to generate the pulse width of the IrDA encoded transport bit stream in low power mode.
• Transmit FIFO: The transmit FIFO is an 8-bit wide, 16-bit deep FIFO memory buffer. CPU data written through the APB interface is stored in the FIFO until read out by the transmit logic. You can disable the transmit FIFO to act like a single-byte holding register.
• Receive FIFO: The receive FIFO is a 12-bit wide, 16-bit deep FIFO memory buffer. The received data and corresponding error bits are stored in the receive FIFO by the receive logic until read out by the CPU through the APB interface. The receive FIFO can be disabled so that it acts as a single-byte holding register.
•Transmit Logic: The transmit logic performs a parallel-to-serial conversion on the data read from the transmit FIFO. According to the programmed configuration in the control register, the control logic outputs a serial bit stream beginning with a start bit, data bits least significant bit (LSB) first, then parity bits, then stop bits.
• Receive Logic: After detecting a valid start pulse, the receive logic performs a serial-to-parallel conversion on the received bit stream. Overrun, parity, framing error checking, and line break detection are also performed, the status of which is displayed along with the data written to the receive FIFO.
• Interrupt generation logic: The UART generates a single maskable high-level active interrupt. The combined interrupt output is also generated as an OR function of the individual interrupt requests. You can use a single combined interrupt with the system interrupt controller which provides another level of masking on a per peripheral basis. This enables you to use modular device drivers that always know where to find the interrupt source control register bits. You can also use individual interrupt requests with the system interrupt controller, which provides masking for each peripheral's output. This way, the global interrupt service routine can read the entire set of sources from one wide register in the system interrupt controller. The time to read from a peripheral register is very important compared to the CPU clock speed in a real-time system.
2.3 Operation
Interface reset:
UART and IrDA SIR ENDEC are reset by global reset signal PRESETn and block specific reset signal nUARTRST. The external reset controller must assert nUARTRST asynchronously using PRESETn and negate it synchronously to UARTCLK. PRESETn must be asserted LOW long enough to reset the slowest block in the system-on-chip, and then be asserted HIGH again. The UART requires PRESETn to be asserted low for at least one PCLK cycle.
Clock signal:
The frequency chosen for UARTCLK must be adapted to the desired baud rate range:
FUARTCLK (min)>=16 (baud rate factor, sampling times) x baud_u rate (max) (send data frequency)
FUARTCLK (max) <= 16 (baud rate factor, sampling times) x 65535 (2^16-1) x baud_rate (min).
For example, for a baud rate range of 110 baud to 460800 baud, the UARTCLK frequency must be in the range of 7.3728MHz to 115MHz. The frequency of UARTCLK must also be within the error limits required for all baud rates. The clock frequency ratio of PCLK to UARTCLK is also limited. The frequency of UARTCLK must not exceed 5/3 times the frequency of PCLK:
FUARTCLK<=5 \3 x FPCLK (apb bus clk)
This allows sufficient time for the received data to be written to the receive FIFO.
2.3.1 uart specific operation
Control data is written to the UART Line Control Register UARTLCR_H. This register is internally 29 bits wide, but is accessed externally via the AMBA APB bus by three writes to register locations UARTLCR_H, UARTIBRD, and UARTFBRD.
UARTLCR_H definition:
• Transfer parameters
• word length
• buffer mode
• Transmission Stop Bits
• Parity mode
• Interrupt generation.
UARTIBRD and UARTFBRD together define the baud rate divisor.
Baud rate configuration:
The baud rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The baud rate generator uses this value to determine the bit period. The fractional baud rate divider allows the use of any clock with a frequency >3.6864MHz as the UARTCLK while still generating all standard baud rates. The 16-bit integer is loaded through the UARTIBRD register. The 6-bit fractional part is loaded into the UARTFBRD register. The relationship between the baud rate divisor and UARTCLK is as follows:
Baud rate divisor = UARTCLK / (16xBaud Rate) = BRDI + BRDF, where BRDI is the integer part and BRDF is the fractional part separated by a decimal point
decimal m=integer(BRDF*2^n+0.5)
Generates the internal clock enable signal Baud16, which is a stream of UARTCLK wide pulses with an average frequency of 16 times the desired baud rate. This signal is then divided by 16 to get the transmit clock. A low number in the baud rate divisor indicates a shorter bit period, while a high number in the baud rate divisor indicates a longer bit period
Data transmission or reception:
Received or transmitted data is stored in two 16-byte FIFOs, and the receive FIFOs have an extra four bits per character for status information.
For transmits, data is written to the transmit FIFO. If the UART is enabled, this causes data frames to start being transmitted using the parameters specified in UARTLCR_H. Data transfer continues until there is no more data in the transmit FIFO. Once data is written into the transmit FIFO (i.e. the FIFO is not empty), the BUSY signal goes high and remains high while the data is being transmitted. BUSY is negated only when the transmit FIFO is empty and the last character (including stop bit) has been transferred from the shift register. BUSY can be asserted HIGH even though the UART may no longer be enabled.
For each data sample, three readings are taken and the majority value is kept. In the following paragraphs, the middle sampling point is defined and a sample is taken on each side of it.
When the receiver is idle as idle (UARTRXD continuous 1, in mark state) and a low level is detected on the data input (start bit has been received), the receive counter (clock enabled by Baud16) starts running, and in normal Data is sampled on the eighth cycle of this counter in UART mode, or the fourth cycle of the counter in SIR mode, to allow for shorter logic 0 pulses (half the bit period).
If UARTRXD is still low on the eighth cycle of Baud16, the start bit is valid, otherwise a wrong start bit is detected and ignored. If the start bit is valid, consecutive data bits are sampled every 16 cycles of Baud16 (i.e. after one bit period) according to the programmed length of the data character. If parity mode is enabled, the parity bit is checked. Finally, a valid stop bit is asserted if UARTRXD is high, otherwise a framing error occurs.
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