[PCIE] Protocol analysis - hot-reset hot reset

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A warm reset of the entire path is specified upstream

When the higher layer instructs certain channels to perform a hot reset (Hot Reset), the following operations will be performed:

All channels in the configured link will send a TS1 ordered set with the hot reset bit (Hot Reset bit) and the configured link number and channel number.

If two consecutive TS1 ordered sets with warm reset bit and configured link number, channel number are received on any channel, then:

LinkUp = 0b (False), indicating that the link is not connected.
If no higher layer indicates that the physical layer remains in the warm reset state, it enters the next state: detection state (Detect).
Otherwise, all channels in the configured link will continue to send TS1 ordered sets with the warm reset bit and the configured link number and channel number.
Otherwise, after waiting for a timeout of 2 milliseconds, enter the next state: detection state (Detect).
in other words:

When the higher layer indicates that a warm reset is required, all configured channels will send a TS1 ordered set with the warm reset bit and configuration information.
If the TS1 ordered set with warm reset bit and configuration information is continuously received on any channel, set LinkUp to False, and decide whether the next state will continue to be in the warm reset state or enter the detection state according to the instructions of the high layer.
If the ordered set of TS1 with the warm reset bit and configuration information is not continuously received, it enters the detection state after waiting for a timeout of 2 milliseconds.

Operations that are not specified upstream for warm reset

For lanes that have not been instructed by higher layers to do a warm reset (i.e., two TS1 ordered sets with a warm reset bit are received consecutively on any configured lane), the following actions will be taken:

LinkUp = 0b (False), indicating that the link is not connected.

If any channel of an upstream port of a switch receives two consecutive TS1 ordered sets with the warm reset bit, all configured downstream ports must transition to the warm reset state as soon as possible.

Any optional crosslinks on the switch are exceptions to this rule and their behavior depends on the specific design of the system.
All channels in the configured link will send a TS1 ordered set with the warm reset bit and the configured link number and channel number.

If two TS1 ordered sets with warm reset bit and configured link number, channel number are received consecutively, the state remains in warm reset state and the 2 millisecond timer is reset.

Otherwise, after waiting for a timeout of 2 milliseconds, enter the next state: detection state (Detect).

hint

Note: Normally, lanes of downstream ports or optional cross-connect ports will be indicated for a warm reset, while lanes of upstream ports or optional cross-connect ports will be passed from resume.idle state to continuous on any configured lane Assert two TS1 ordered sets of reset-warm bits to enter the reset-warm state.

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Origin blog.csdn.net/qq_21688871/article/details/131594642