0. Preface
I'm a rookie, and I haven't published an article for a long time. As usual, today I recommend a book "The Outsider". Don't be like the protagonist and think that nothing makes sense.
Table of contents
1.1 Homogeneity and heterogeneity
1.2.1 Symmetric multiprocessing architecture (SMP)
1.2.2 Asymmetric Multiprocessing Architecture (AMP)
1.2.3 Boundary Multiprocessing Structure (BMP)
1. SMP and AMP Architecture
In 1971, Intel Corporation designed a 4-bit 4004 microprocessor, which was the first commercial processor. Soon Intel introduced the 8-bit 8008 processor and the 16-bit 8086 processor. At that time, the 4004 Chip, 8008 chip, and 8086 chip all have only one core (single-core CPU). With the increase in demand and power consumption, it was gradually found that one core was not enough, so two or more cores were built on one chip. Core, and then turned to the development of multi-core processors. Multi-core CPUs have higher computing density and stronger parallel processing capabilities, and the multi-core trend has changed the face of IT computing.
1.1 Homogeneity and heterogeneity
From the perspective of hardware, multi-core processors can be divided into homogeneous and heterogeneous, as shown in the figure below.
Isomorphic (left) and heterogeneous (right)
1.1.1 Isomorphism
If all CPUs or cores have the same architecture, it is called isomorphic. For example, Samsung's Exynos4210, Freescale's I.MX6D and TI's OMAP4460, they have two Cortex-A9 cores with the same architecture, all of which are isomorphic.
1.1.2 Heterogeneity
If the architecture of all CPUs or cores is different, it is called heterogeneous. For example, ST's STM32MP157 has two Cortex-A7 cores and one Cortex-M4 core, Xilinx's ZYNQ7000 series has two Cortex-A9 cores and FPGA, TI's Da Vinci series TMS320DM8127 has a DSP C674x core and a Cortex-A8 core, these processors have cores with different structures, so they are all heterogeneous.
1.2 SMPs and AMPs
From the perspective of software, the operating system system of the multi-core processor platform includes: SMP (Symmetric multiprocessing, symmetric multiprocessing) structure, AMP (Asymmetric Multi-Processing, asymmetric multiprocessing) structure and BMP (bound multi-processing, Boundary multiprocessing) structure.
1.2.1 Symmetric multiprocessing architecture (SMP)
The SMP structure means that only one operating system (OS) instance runs on multiple CPUs, one OS equally manages each core, distributes workloads to each core, and all cores in the system equally access memory resources and peripheral resources. Because the core structures of heterogeneous processors are different, if an OS manages different cores, it is more complicated to implement, so generally, homogeneous processors run under the SMP structure. Various operating systems such as Windows, Linux, and Vxworks support the SMP structure.
As shown in the figure below, under the SMP structure, an OS is responsible for coordinating two processors, and the two processors share memory. The addresses of the applications (APP1 and APP2) running on each core are the same. Through the MMU (Memory Management Unit, memory management unit) maps them to different locations in main memory.
SMP structure
1.2.2 Asymmetric Multiprocessing Architecture (AMP)
The AMP structure means that each core runs its own OS or an independent instance of the same OS, or does not run an OS, such as running bare metal, each core has its own independent memory space, and can also share part of the memory space with other cores. The cores run different tasks relatively independently, but one core is the main core, which is responsible for controlling the operation of other cores and the entire system, while other cores are responsible for "cooperating" with the main core to complete specific tasks. Here, the main core is called the main processor, and the other cores are called coprocessors or remote processors. The biggest feature of this structure is that each operating system has its own exclusive resources, and other resources are designated by the user to be shared by multiple systems or specially allocated to a certain system for use, and the communication between systems can be completed through shared memory.
The following figure is a resource diagram of STM32MP157. The Cortex-A7 core of STM32MP157 can run the Linux operating system, and the Cortex-M4 core can run bare metal or other RTOS (real-time operating system), RTOS such as OneOS, FreeRTOS, RT-Thread and UCOS. Both Cortex-A7 and Cortex-M4 have their own exclusive resources and shared resources. These resources are allocated by users, and the dual cores can communicate through shared memory.
In AMP system design, two problems generally need to be solved:
(1) Life cycle management (kernel startup sequence) issues;
(2) Inter-kernel communication issues.
The best way to configure the AMP system is to use a unified framework that meets both control and communication requirements, and OpenAMP is the most widely used standard framework for current multi-core architectures, and many chip suppliers provide implementations of OpenAMP. Based on OpenAMP, the life cycle management is realized through Remoteproc, and the inter-kernel communication is managed through RPMsg. We will introduce the implementation methods of the two later.
1.2.3 Boundary Multiprocessing Structure (BMP)
BMP is similar to SMP in that an operating system manages all CPU cores at the same time, but developers can specify a task to be executed in a certain core, so the BMP structure will not be described in detail here.
There are obvious differences between AMP and SMP mentioned earlier, but there is also a connection between the two. For example, on a chip, multiple cores with the same architecture may be configured as an SMP subsystem, while other cores run It is another operating system, which is an AMP structure from an overall point of view. From a logical point of view, this SMP subsystem looks like a single core, which can be regarded as included in this large AMP system. For example, the two Cortex-A7 cores of STM32MP157 run the same Linux operating system. These two Cortex-A7 cores can be regarded as an SMP subsystem, and the Cortex-M4 core can run bare metal or RTOS. Then the STM32MP157 The chip as a whole is an AMP structure.
2. Summary
The above are from punctual atom, who is studying heteronuclear communication recently. The explanation is good and easy to understand.
It is much more effective to dig a certain point deeply than to dabble in a very shallow understanding, because what you have learned through digging deeply is the whole through thinking, which is very important for future growth.