What do you learn in the practical course of the whole process project?
This time, [ASIC chip design full-process project practical course] is launched, based on the IPA image processing accelerator, taking the enterprise-level real ASIC project as a case, students can participate in the full-process project practice, and 65nm real tape-out!
As we all know, looking at the entire IC master circle, there are only a few colleges and universities that are capable of arranging tape-outs. Therefore, the students who have participated in the tape-out seriously are really rare.
This time, the IC Cultivation Institute launched a project that can be taped to help students in need solve this problem.
This course is based on IPA, namely "Image Processing Accelerator", which is called Image Processing Accelerator in Chinese.
This is a specially designed chip module, which is mainly used to complete tasks such as image data collection, input, storage, gridding/windowing and image format conversion, and can realize image processing acceleration to provide high-performance image processing functions .
Image processing acceleration is one of the cutting-edge subdivision research fields in the industry. For example, IC giant Nvidia is a senior player in this field.
Next, let's take a look at what the IPA project is. What knowledge skills and advantages can be obtained after learning?
Let me put it here: Understand the actual combat of tape-out projects (specific introduction)
Learn about the IPA project
Image data collection : The IPA module realizes the efficient collection of original image data through the interface with the infrared image sensor. It is able to handle image data of different types and sources, ensuring data accuracy and integrity.
Data storage : The IPA module has a data cache function, which can temporarily store a large amount of image data. Through the caching mechanism, it can balance the flow rate difference of image data and ensure the continuity and stability of subsequent processing steps.
Gridding/windowing : In order to improve processing efficiency and flexibility, the IPA module has the function of gridding/windowing image data. It is able to divide image data into small image blocks and select regions of interest for processing, thereby reducing the computational load of subsequent algorithms.
Efficient data processing : Through a series of preprocessing and optimization steps, the IPA module can convert image data into a data format that can be directly used by specific algorithms. This includes operations such as data normalization, resizing, padding, and normalization to improve processing efficiency and accuracy.
DDR writing : The image data processed and converted by the IPA module is finally written into the DDR. DDR is a high-speed random access memory, which provides large capacity and fast data access capability, and provides a high-quality data basis for subsequent image processing and analysis.
What are the project advantages?
Efficient image data collection : The IPA module can efficiently collect various types of image data, image data transmitted through infrared images. This ensures that the system can handle a variety of images and adapt to the needs of different application scenarios.
Data storage and gridding/windowing functions : The IPA module has data storage and gridding/windowing functions, which can process a large amount of image data and divide it into image blocks of appropriate size. This helps improve the processing efficiency and throughput of the system and provides suitable data input for subsequent processing steps.
Flexible integration capability : The IPA module has flexible integration capability and can be seamlessly integrated with other modules and components to build a complete image processing system. It can perform efficient data interaction with data processing modules, DDR memory and other peripherals, providing powerful image processing functions for the system.
High performance and real-time processing : The IPA module is designed and optimized for high performance and real-time image processing. Through efficient algorithm and hardware implementation, the IPA module can process a large amount of image data in a short time and meet the requirements of real-time processing.
The above project introduction and project advantages are to help us fully understand the courses and professional knowledge from a professional perspective.
Simple to understand - it is to help students who have no projects or projects with low difficulty in school, quickly run through the whole process of digital chip projects, and make a 65nm tape-out project that can be written on their resumes!
highlights
It is undoubtedly a breakthrough attempt to appear in front of the public in the form of the whole process of the project for the first time! This is a great opportunity for students and students who want to enter the IC industry.
Covering three major aspects of digital design
This course will use the IPA (Image Processing Accelerator) project to draw up a spec. From digital design, to functional verification, to back-end layout and routing, it runs through the teaching project.
Students will be exposed to the three major links of digital design, functional verification, and back-end implementation of the IPA project. For students who have difficulty choosing IC design positions, it greatly reduces the cost of selection and the risk of career planning!
65nm Tape-out Project Blessing
Tape-out can be called "a coming-of-age ceremony for newcomer chip engineers", but at present, it is difficult for most colleges and universities in China to provide tape-out opportunities, which is also part of the disconnect between production and education.
Short learning period, more efficient
The course period is 4 months, and you can quickly run through the digital chip design process and learn more efficiently.
The main focus is on doing projects, and will not spend too much time explaining basic principles and knowledge. Therefore, it is only applicable to postgraduates of IC majors who have a knowledge base.
details
Method : recording + live broadcast
Period : 4 months
Suitable for the crowd : Graduate students in school (microelectronics, integrated circuits, electronics and other related majors, those who have digital, electronic, analog, and Verilog basics)
outline
Instructors
Design: Pual, Kevin, Bob
Paul
Background: Ph.D. from George Mason University
Experience: 15 years working experience in digital design and architecture
Resume: Worked for Qualcomm as an architecture engineer.
He has a deep understanding of AXI high-performance design, advanced HDL design, functional programming, Serdes high-performance design, PCIe, and low-power design, and is proficient in the whole process of digital design.
Kevin
Background: Master degree from University of Chinese Academy of Sciences
Experience: 10 years working experience in digital front-end design
Resume: Worked in ZTE Microelectronics Research Institute as an expert front-end design engineer.
With rich project experience, he has been engaged in module design and architecture design for a long time. Participate in the design of a variety of 5G base station core chips; have a deep understanding of front-end design, verification, timing optimization and power consumption analysis.
Bob
Background: Master's degree from University of Electronic Science and Technology of China
Experience: 10 years of experience in digital front-end design and architecture
Resume: Worked at Nvidia as a senior digital design engineer.
Participated in the architecture design of a variety of chips, and has a deep understanding of digital-analog hybrid design, digital front-end and digital back-end, integrated STA, and low-power design.
Verification: Xilin, Teacher Chen, Nancy
Xilin
Background: Master's Degree in Microelectronics from Peking University
Experience: more than 10 years of digital IC verification work experience
Resume: Worked for Huawei as an expert verification engineer.
Obtained a number of patents. Responsible for the verification of smart network card chips in the IOC field, and has experience in successful tape-out of many large-scale chips. Proficient in Fiber Channel protocol, ARM AMBA bus protocol, cache space management implementation; proficient in semiconductor power device design process, chip process flow; proficient in Perl, VBA and other scripting languages.
Teacher Chen
Background: Master degree from Xi'an Jiaotong University
Experience: more than 10 years of digital IC verification work experience
Resume: Worked in Huawei HiSilicon as a senior digital verification engineer.
Participate in processor-core cache consistency verification and PCIe Vip integration verification, responsible for AI chip-convolutional neural network module verification; proficient in Cache consistency verification, SoC verification, AI chip verification, PCIe/AMBA and other bus verification.
Nancy
Background: Master degree in microelectronics from Xidian University
Experience: more than 10 years of digital IC verification work experience
Resume: Worked in ZTE and Intel as a senior chip verification engineer.
Responsible for the verification of baseband processing chips and mobile phone chips. He has successful tape-out experience of various chips. He is proficient in video decoding, audio processing and other module verification, SOC verification, USB and AMBA bus verification, and is proficient in scripting languages such as perl and python.
Backend: Teacher Wei, Teacher Tang, Xiao Y
Teacher Wei
Background: Master's degree from Northwest University, corporate mentor at Xidian University
Experience: More than 20 years of digital IC backend experience
Resume: Worked in Infineon and Aerospace Research Institute as an expert digital back-end engineer.
Has rich 7/5nm tape-out experience. Participate in the signoff work of various chips; have in-depth research on back-end timing convergence, logic synthesis, layout and routing, and physical verification, and have rich experience in back-end full-process design.
Teacher Tang
Background: Master's Degree in Integrated Circuits, University of Auckland, New Zealand
Experience: 8 years of experience in digital backend design
Resume: Worked in Institute of Microelectronics and Synopsys as a senior digital back-end design engineer.
Responsible for ICC2 product verification, EDA tool evaluation and process design and development. Proficient in scripting language, develop automation scripts to improve the efficiency of IC design process.
small Y
Background: Ph.D. in Integrated Circuit Design, Xidian University
Experience: 10 years of experience in digital backend design
Resume: Worked at Samsung Semiconductor as a digital back-end senior engineer.
Participate in the top-level STA work of ultra-large digital chips with multiple advanced technologies, and realize the full process of multiple module-level physics, involving floorplan to route, as well as timing signoff, PV verification, LEC verification, and PA verification. Rich constraint writing and timing analysis capabilities.
Let me put it here: Understand the actual combat of tape-out projects