K210 Development Example - Watchdog Timer (WDT)

Watchdog Timer (WDT)

1. WDT introduction

WDT provides recovery functions when the system fails or becomes unresponsive.

The WDT is a slave peripheral of the APB and is part of the "Synchronization Hardware Component Design". There are two WDTs, namely
WDT0 and WDT1. The main modules of the watchdog timer are:

• One APB slave interface
• A register block for current counter synchronization
• An interrupt/system reset block and logic control circuit that decrements the counter
• A synchronous clock domain to support asynchronous clock synchronization

The watchdog timer supports the following settings:

• APB bus width configurable to 8, 16 and 32 bits
• The clock counter decrements from a set value to 0 to indicate the termination of time
• Optional external clock enable signal to control the count rate of the counter
• A clock timeout WDT can perform the following tasks:
  • Generate a system reset signal
  • First an interrupt is generated, even if the bit has been cleared by the interrupt service, and second it generates a system reset signal
• Duty Cycle Programmable Adjustment
• Programmable and hardware set counter start value
• Counter Recount Protection
• Suspend mode, only when external suspend signal is enabled
• WDT accidental disabling protection
• Test mode for counter function testingÿ