【ETH】Ethernet----PHY Chip LAN8720A----Schematic Diagram

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1. LAN8720A----Introduction

LAN8720A is a low-power 10/100M Ethernet PHY layer chip, the I/0 pin voltage complies with the EEE802.3-2005 standard, supports communication with the Ethernet MAC layer through the RMI interface, and has built-in 10-BASE-T/100BASE-TX Full duplex transmission module, supports 10Mbps and 100Mbps.

LAN8720A can auto-negotiate the best connection mode (speed and duplex mode) with the destination host, and supports HPAuto-MDIX automatic flip function, which can change the connection to direct connection or cross-connection without changing the network cable.

The main features of LAN8720A are as follows:

• High-performance 10/100M Ethernet transmission module
• Supports RMII interface to reduce pin count
• Supports full-duplex and half-duplex modes
• Two status LED outputs
• 25M crystal can be used to reduce cost
• Support auto-negotiation mode
• Support HP Auto-MDIX automatic flip function
• Supports SMI serial management interface
• Support MAC interface

LAN8720A----system block diagram

LAN8720A----internal structure

2. LAN8720A----pin description

LAN8720A----pin diagram

LAN8720A----pin description table

pin number	symbol	name	illustrate
1	VDD2A	+3.3V channel 2 analog port power supply	+3.3V analog port supply for channel 2 and internal regulator
2	LED2	Link speed LED indication	When operating at 100 Mbps, this pin will be driven active. When operating at 10 Mbps, or during line isolation, this pin is inactive.
	nINTSEL	14-pin (nINT/REFCLKO) function select configuration pins	When the pin is floating or pulled high to VDD2A (default), REF_CLK input mode, nINT/REFCLKO is active low interrupt output. When the pin is pulled low to ground, REF_CLK output mode, nINT/REFCLKO is the clock source of REF_CLK.
3	LED1	Link activity LED indication	This pin is driven active when a valid link is detected and blinks when activity is detected.
	REGOFF	Regulator off configuration strap	This strap is used to disable the internal 1.2V regulator. When the regulator is disabled, an external 1.2V must be supplied to VDDCR. When REGOFF is pulled high to VDD2A through an external resistor, the internal regulator is disabled. When REGOFF is left floating or pulled low, the internal regulator is enabled (default).
4	XTAL2	External crystal output	External crystal output
5	XTAL1	External crystal input	External crystal input
	CLKIN	external clock input	Single-Ended Clock Oscillator Input. Note: XTAL2 must not be connected when using a single-ended clock oscillator.
6	VDDCR	+1.2V digital core supply	Powered by the on-chip regulator unless configured for regulator-off mode via the REGOFF strap. Note: 1 μF and 470 pF decoupling capacitors in parallel to ground should be used on this pin.
7	RXD1	receive data 1	Channel 1 of the transceiver on the receive path.
	MODE1	PHY working mode 1 configuration strap	This configuration strap is used with MODE0 and MODE2 to set the default PHY mode.
8	RXD0	Receive data 0	The transceiver is channel 0 on the receive path.
	MODE0	PHY working mode 0 configuration strap	This configuration strap is used with MODE1 and MODE2 to set the default PHY mode.
9	VDDIO	+1.6V to +3.6V Variable I/O Supply	+1.6V to +3.6V Variable I/O Supply
10	RXER	receive error	When asserted, this signal indicates that an error has been detected in the frame currently being transmitted from the transceiver.
	PHYAD0	PHY address 0 configuration strap	This configuration strap is used to set the SMI address of the transceiver.
11	CRS_DV	Carrier sense/receive data valid	When asserted, this signal indicates that the receiving medium is not idle. When a 10BASE-T packet is received, CRS_DV is asserted, but RXD[1:0] remains low until an SFD byte (10101011) is received. Note: According to the RMII standard, in 10BASE-T half-duplex mode, the transmitted data is not looped back to the receive data pin.
	FASHION2	PHY working mode 2 configuration strap	This configuration strap is used with MODE0 and MODE1 to set the default PHY mode.
12	MEDIUM	SMI data input/output	Serial management interface data input/output
13	MDC	SMI clock	Serial Management Interface Clock
14	nINT	interrupt output	Active low interrupt output. Place an external pull-up resistor to VDDIO
	REFCLKO	Reference clock output	REFCLKO can be selected through the nINTSEL configuration strap. This optional 50MHz clock output is derived from a 25MHz crystal oscillator.
15	nRST	external reset	System reset. This signal is active low.
16	CHEN	send enable	Indicates that there is valid transmit data on TXD[1:0].
17	TXD0	send data 0	The MAC uses this signal to send data to the transceiver.
18	TXD1	send data 1	The MAC uses this signal to send data to the transceiver.
19	VDD1A	+3.3V channel 1 analog port power supply	+3.3V analog port power supply for channel 1
20	TXN	Ethernet TX/RX negative channel 1	Transmit/Receive Negative Channel 1
21	TXP	Ethernet TX/RX positive channel 1	Send/receive positive channel 1
22	RXN	Ethernet TX/RX negative channel 2	Transmit/Receive Negative Channel 2
23	RXP	Ethernet TX/RX positive channel 2	Send/receive positive channel 2
24	RBIAS	External 1% bias resistor input	This pin requires a 12.1 kΩ (1%) resistor to ground.

3. LAN8720A----Circuit Schematic Diagram

1. REF_CLK input mode

In REF_CLK input mode, 50 MHz REF_CLK is driven on the XTAL1/CLKIN pin.
When using this mode, a 50 MHz clock source must be provided external to the device for REF_CLK, which is driven to the MAC and PHY.

Provide an external 50 MHz clock source for REF_CLK, as shown in the figure below:

2. REF_CLK output mode

To reduce the BOM cost, the device is equipped with the function of generating the RMII REF_CLK signal from a low-cost 25 MHz fundamental frequency crystal.
These crystals are less expensive than 3rd harmonic crystals that typically require 50 MHz. The MAC must support an external clock to use this feature.

Generate REF_CLK through a 25 MHz crystal oscillator, as shown in the following figure:

Generate REF_CLK through an external 25 MHz clock source, as shown in the figure below:

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To be continued. . . . .