Explain the IO control method in detail from the meter group and the operating system

IO control mode

In fact, IO is mentioned in both the operating system and the meter group. These two contents have different emphases, and there is a great overlap, so I will sort it out here.

In the operating system, I talked about the basic process, and the meter group also talked about various interface circuits.

1. Direct program control mode

In the direct program control mode, the user process directly controls the main memory or the information transfer between the CPU and peripheral devices. **Direct program control mode is also called inquiry mode, or busy/wait mode. **Test the busy/busy flag bit of the I/O device through the I/O command or query command to determine whether to exchange a character or a word between the main memory and the peripheral device.

The workflow of the direct program control method is as follows:

• ① When the user process needs to input data, send an I/O command to the controller through the CPU, start the device to input data, and set the busy/busy status in the status register to 1 at the same time
• ② The user process enters the test waiting state. During the waiting process, the CPU continuously checks the busy bit in the status register of the peripheral device with a test command, and the peripheral device only checks the busy bit in the data register of the controller after the data is transmitted to the controller. is 0,.
• ③ The processor takes out the data in the data register, sends it to the designated unit of the main memory, completes the I/O operation of one character, and then performs the I/O operation of the next data

All in all: there will be an IO control process, and the CPU will always be stuck in a query cycle, waiting for the IO device to prepare the data.

Although the direct program control method is simple and does not require much hardware support, due to the speed mismatch between the high-speed CPU and the low-speed I/O device, the CPU and peripheral devices can only work serially, making the CPU absolutely Most of the time is spent waiting for the completion of the I/O operation cycle test, resulting in a great waste of CPU, peripheral equipment can not be used reasonably, the efficiency of the entire system is very low. Therefore, this I/O control method is only suitable for systems with slower CPU execution speed and fewer peripheral devices.

2. Interrupt-driven control mode

The interrupt request of the IO device triggers the external interrupt of the CPU.

In order to reduce the waiting time of the CPU under direct program control and improve the parallelism of the system, the system introduces an interrupt mechanism. After the introduction of the interrupt mechanism, the peripheral device sends an interrupt request to the CPU only when the operation ends normally or abnormally.

In the process of inputting each data by the I/O device, the parallel work of the CPU and the I/O device is realized to a certain extent without the intervention of the CPU. Only when a data input or output is completed, the CPU needs to spend a very short time for interrupt processing.

The article referred to here is not clearly written. In fact, when IO is interrupted, first of all, the CPU needs to generate an interrupt to start our IO device, and then we think that the device is always on. Then the CPU continues to do its own thing, while the device is also doing its own thing. That is to say, the preparation of data by the IO device has nothing to do with the CPU. When the data preparation of the IO device is completed, an interrupt request will be issued, requiring the CPU to process the data prepared by the IO device (entering the interrupt handler, but many times It is to ask the CPU to access the memory to store the data in).

(I won’t go into detail about the detailed process of the interruption, leave it to the interruption)

Existing problems: Since the I/O operation is directly controlled by the CPU, an interrupt occurs every time a character or word is transmitted, which still takes up a lot of CPU processing time, so it can be reduced by adding buffer registers for peripheral devices to store data. number of interruptions. (Staging of the data preparation process is possible)

The characteristics of the above two methods are CPU-centered, data transmission is realized through a program, and the transmission means of software limits the speed of data transmission.

3. Direct memory access control method

The direct memory access control method is also called the DMA (Direct Memory Access) method. In order to further reduce the CPU's intervention on I/O operations, and prevent data loss caused by too many parallel operating devices, which make the CPU too late to process or the speed does not match, a DMA control method is introduced. Under the control of the DMA controller, by stealing or misappropriating the bus control right, a direct data exchange channel is opened between the device and the main memory , and data is exchanged in batches without CPU intervention.

The most important thing is to open up the DMA channel, and the IO device no longer uses the CPU to store it in the memory.

In fact, I always like to add DMA channels, but the DMA here has no channels, so I changed my name.

Features of DMA mode:

• ① Data transmission takes data blocks as the basic unit, and the CPU plans which block to store in the memory at the beginning .
• ② The transmitted data is directly sent from the device to the main memory, or directly output from the main memory to the device.
• ③ The intervention of the CPU is only required at the beginning and end of the transfer of one or more data blocks, while the transfer of the entire block of data is completed under the control of the controller.
  • That is to say, the DMA method requires the CPU to give us where the data is stored in the memory. It can only be a continuous space, and the prediction must be completed at the very beginning.

Compared with the interrupt-driven control mode, the DMA mode reduces the intervention of the CPU on I/O operations, and further improves the degree of parallel operation between the CPU and I/O devices.

The DMA method has simple lines and low prices, and is suitable for batch data transmission between high-speed devices and main memory. This method is used for fast devices in small and microcomputers, but its functions are poor and cannot meet complex I/O Require.

Three ways to use DMA channel

First of all, why should we consider this? The problem with this is that the main memory can only be accessed by one device at a time. Both the DMA and the CPU directly interact with the main memory, so how do we allocate it.

1. stop CPU from accessing main memory
   1. This is very violent, and the DMA will send a signal to the CPU to tell the CPU to stop.
2. cycle stealing
   1. Actually bus occupancy and main memory cycles
   2. When the IO sends a DMA request, it stops for a few main memory cycles and the CPU occupies the main memory (without interruption)
3. alternate access
   1. This generally requires a CPU instruction (work in the book, but I think it is an instruction) cycle to be longer than the storage cycle of the main memory. In a working cycle, there will be no memory access, and the part that does not access memory will be fixed to DMA.

DMA interface composition

It can only be said that the meter group is really much smaller than the operating system.

name
AIR(SEA)	Old acquaintance, memory address register	When the CPU activates the DMA mode, it must first specify the first address of the stored memory
WC	word counter	It is used to record how many words are stored in total. It is set when the CPU is activated, and it keeps decreasing (it refers to the value, because it may be a complement), and an interrupt is triggered when it reaches 0.
BR	data buffer register	Needless to say this
DMA control logic		One is responsible for applying to the CPU for initialization, and the other is responsible for all subsequent processes, such as interface register modification, addressing, device signal identification and sending.
interrupt mechanism	Responsible for issuing interrupt signals
DAR Device Address Register	Registers for IO device information, because we also have to choose IO devices.	Device number, device memory information. (Pay special attention that the external memory is also an IO device, so the disk data address may be stored here)

4. Channel control mode

To sum up: the channel is also a processor, and the CPU sends the management work of the interaction between the IO device and the memory (the first address of the management program + the number of the IO device) to the channel. This management work is described by the channel program in the memory.

Although the DMA method has significantly reduced CPU intervention compared to the interrupt method, that is, the intervention in units of bytes (bytes) has been reduced to the intervention in units of data blocks. **But every time the CPU issues an I/O instruction, it can only read/write a continuous data block. **When we need to read multiple data blocks at a time and transfer them to different memory areas, or vice versa, the CPU needs to issue multiple I/O instructions and perform multiple interrupt processing to complete.

The channel control method realizes the parallel operation of the CPU, channel and I/O devices , thereby more effectively improving the resource utilization rate of the entire system. For example, when the CPU wants to complete a group of related read (or write) operations, it only needs to issue an I/O instruction to the I/O channel, pointing out the first address of the channel program to be executed and the I/O device to be accessed , after the channel receives the instruction, the I/O task specified by the CPU can be completed by executing the channel program. It can be seen that the channel only sends an I/O interrupt request to the CPU at the beginning and end of the I/O operation, which further reduces the degree of CPU intervention compared with the previous control method.

1. Introduction of channel control mode

The channel control method is similar to the DMA control method, and it is also a memory-centered control method that directly exchanges data between the device and the memory.

Compared with the DMA control method, the channel method requires less CPU intervention, and one channel can control multiple devices, thereby further reducing the CPU burden.

A channel is essentially a simple processor that is responsible for input and output control, has the ability to execute I/O instructions, and controls I/O operations by executing channel I/O programs.

• Channel, independent of the CPU, is a processor responsible for input and output control, which controls the direct data exchange between the device and the memory. Has its own channel instructions that are started by the CPU and signal an interrupt to the CPU at the end of the operation.

The instruction system of the channel is relatively simple, generally only data transmission instructions, equipment control instructions and so on.

The I/O channel control method is the development of the DMA control method, which further reduces the CPU's participation in the control of data transmission, that is, the intervention of reading/writing a data block is reduced to the reading of a group of data blocks. / Write and intervene about the control and management of units. At the same time, parallel operations of CPUs, channels and I/O devices can be realized, thereby more effectively improving resource utilization of the entire system. In the channel control mode, the CPU only needs to issue a start command to indicate the operation required for the channel and the I/O device used, and the command can start the channel and make the channel call out the corresponding channel program from the memory for execution.

Take data input as an example: when the user process needs data, **CPU issues a start command to indicate the I/O operation to be performed, the device and channel to be used. **When the corresponding channel receives the startup instruction from the CPU, it reads out the channel program stored in the memory, executes the channel program, and controls the device to transfer the data to the designated area in the memory. While the device is taking input, the CPU can do other work. **When the data transfer is finished, the device controller sends an interrupt request to the CPU. ** After the CPU receives the interrupt request, it turns to the interrupt handler for execution, and returns to the interrupted program after the interrupt ends.

• Advantages: The channel control method solves the independence of I/O operations and the parallelism of the work of each component. Free the CPU from tedious input/output operations. After adopting the channel technology, not only the parallel operation of the CPU and the channel can be realized, but also the parallel operation between the channels can be realized, and the peripheral devices on each channel can also be operated in parallel, thereby improving the efficiency of the entire system.
• Cons: Higher cost due to more hardware (channel processors) required. The channel control method is usually used in the occasion of large data interaction.

The direct program control method and the interrupt program control method are suitable for data transmission of low-speed devices, while the DMA method is suitable for data transmission of high-speed devices, but a DMA controller can only control a small number of similar devices, which is far from satisfying the needs of large-scale computer systems. needs. Usually, a large computer needs to connect a large number of high-speed and low-speed devices, and the channel control method can meet this requirement. (The main difference between DMA and channel control methods - whether it can meet the needs of large computer systems that can handle both high-speed devices and low-speed devices)

2. Channel program

The channel implements the control of the I/O device by executing the channel program and working with the device controller. A channel program is composed of a series of channel instructions. Channel instructions and general machine

The instructions are different, and each of its instructions contains the following information:

• 1) Opcode. The operation code specifies the operation performed by the instruction, such as read, write, control and other operations.
• 2) Memory address. The memory address indicates the first address of the memory when characters are sent into the memory (read operation) and taken out of the memory (write operation).
• 3) Count. This information indicates the number of bytes of data to be read/written by this instruction.
• 4) Channel program end bit P. This bit is used to indicate whether the channel program has ended. P=1 means this instruction is the last instruction of the channel program.
• 5) Record end flag R. R=0 indicates that the data processed by this channel instruction and the next instruction belong to the same record; R=1 indicates that this is the last instruction to process a certain record.

The difference between channel control mode and DMA control mode:

• 1) In the DMA control mode, the CPU is required to control the size of the transmitted data block and the memory address to be transmitted; in the channel control mode, these information are controlled and managed by the channel.
• 2) One DMA controller corresponds to one device and memory to transfer data, and one channel can control the data exchange between multiple devices and memory.

The difference between an I/O channel and a general processor: the instruction type of an I/O channel is single, and the commands it can execute are mainly limited to instructions related to I/O operations; the channel does not have its own memory, and the channel program executed by the channel It is placed in the memory of the host, that is to say, the channel shares memory with the CPU .