Operating system (IO management)

Operating system (IO management)

A, IO concept

IO is the I / O (input / output)

IO device is the ability to input data to the computer, the computer or the external device may receive the output data belongs to the hardware components of the computer

Daily life, the most typical IO devices is summarized as follows:

• Keyboard, character input device (input)
• A display, an output device (output)
• Removable hard disk, both the input device and can output

IO device classification

• By using the characteristics of classification

  • Interactive class device (data transmission speed)
  • Storage device (data transfer speed)
  • A network communication device (data transfer speed between the two above)

  

• Classified according to the transmission rate

  • Low-speed device (several to several hundred bytes per second)
  • Device speed (a few thousand to tens of thousands of bytes per second)
  • High-speed devices (gigabytes per second to thousands)

• Units in accordance with the exchange of classified information

  • Block device (transmission speed, addressable)
  • Character device (slow transmission, non-addressable, often using an interrupt driven mode)

Two, IO control

2.1IO controller

CPU IO device can not directly control the mechanical parts, and therefore also the IO device with an electronic component as an intermediary between the CPU and the IO device mechanical components, for implementing the control of the CPU of the device , the electronic component is IO controller, also known as a controller for the device, the CPU controller controls IO, IO controller to control the IO equipment

Function IO controller

• And receiving identification instruction issued by the CPU
  • IO controller control registers corresponding to the respective commands and parameters stored came cpu
• To report device status cpu
  • IO controller, a corresponding status register to record the current state of the IO device
• Data Exchange
  • IO controller corresponding data register
    • Output data register for temporarily storing the data sent by CPU, then the controller after transmitting device
    • When the input data register for temporarily storing data sent by the apparatus, after removal of cpu data from the data register
• Address Recognition
  • To distinguish each device controller registers, but also to set respective registers a specific address, the IO controller via the address provided by the CPU to determine cpu to read / write registers which

The composition of the IO controller

There are said to give the above registers addressable device controller to distinguish the respective registers

Addressing modes:

• Memory-mapped IO (registers and memory controller integrated presentation)

  

• Independent addressing register (register independently compiled controller)

2.2IO control

2.2.1 direct control program

Complete a read process

• CPU issues a read command to the start control device, and reports itself
• Polling controller CPU checks the status register, the status register when the apparatus becomes ready state, ready to read data from the device
• After the equipment ready data to the data register
• CPU reads the data from the data register to register cpu
• CPU CPU register data into memory
• Determining whether the data will continue to read, also need to continue to read the read command is issued cpu

cpu frequency interference

CPU frequency of intervention is very frequent, IO operation before the start, after the completion of all required CPU intervention, and while waiting for IO completion of the CPU need to constantly check the device status poll

Data transfer unit

Data transfer unit is a word

Data flow

• Read (data input): IO Device - "CPU -" Memory
• Write (data output): Memory - "CPU -" IO device

Reading and writing each word cpu needs help

The main drawback of the main advantages and

• Advantages: simple
• Drawback: cpu utilization is low, cpu and serial IO device can only work

2.2.2 interrupt-driven mode

Complete a read process

After the introduction of interrupt mechanism, because the IO devices is very slow, so read and write commands issued in the CPU, IO can wait for the process to block, switch to another process execution (CPU to do other things) After completion of IO, IO control register is sent to the CPU an interrupt signal, the CPU detects the interrupt signal, the process saves the current context is switched to execute the interrupt handler processes the interrupt, the interrupt handling process, the CPU reads a word from the IO controller cpu and then put into memory, then, CPU wait for the process to restore the context of the IO, then continue

In fact equivalent, CPU process is currently blocked waiting for IO in the read command issued to the IO controller after, let yourself IO device IO device, the device will wait until the data into the data register of the IO controller, the IO controller CPU issues an interrupt, let cpu to fetch data into memory

cpu frequency interference

Before the beginning of each IO operation, after the completion of all required CPU intervention

While waiting for IO completion of the CPU can switch to another process execution

Data transfer unit

Data transfer unit is a word

Data flow

• Read (data input): IO Device - "CPU -" Memory
• Write (data output): Memory - "CPU -" IO device

The main drawback of the main advantages and

• Advantages: Compared with the control program directly, in the interrupt driven mode, the controller will automatically report IO through the IO completion interrupt signal, the CPU does not need to stop polling, cpu and IO devices can work in parallel, CPU utilization, may be raised
• Shortcomings, frequently interrupt processing will consume more CPU time

2.2.3DMA way

DMA (direct memory access)

• When the block data transfer unit, not a test word, a word transfer
• Data flow: the device directly to the device directly to memory or memory

• The DR (Data Register): temporarily storing data from the device to memory, or from memory to the device
• The MAR (Memory Address Register): When an input, the MAR indicates what data should be placed in the memory location, the output, the MAR represents the data to be output on the memory of what position
• DC (data counter): the number of bytes remaining to be read / write
• CR (Command / Status Register): storing state information for an IO command is issued to the CPU, or equipment

• To indicate the operation of the CPU, such as read, and explain how to read the data, what data should be stored in a memory location, the address data on an external device

• After the controller completes the work of reading and writing CPU data request made after the completion of transmission of the data block, before issuing an interrupt signal to the CPU

• dma memory and can directly interact

cpu frequency interference

At the beginning and end to make one or more data transmission blocks, only need to intervene cpu

The main drawback of the main advantages and

• Advantages: the data transmission efficiency, and parallelism cpu IO devices mentioned lifting
• Disadvantage: CPU issuing an IO per instruction, access to only one or more contiguous data blocks, if you want to read and write data stored in a plurality of discrete blocks, or write data to different memory areas, respectively, the CPU to issue multiple Article IO command. Interrupted multiple times to complete the process

2.2.4 channel control

Channel, independent of the CPU dedicated input processor output control, additional control devices to exchange data directly with memory, with its own passage instructions that are initiated by the CPU, and sends an interrupt signal to the CPU at the end of the operation.

CPU control channel achieved, the three passages and IO devices operated in parallel, thereby more effectively improving the resource utilization of the system, when the CPU to complete a set of read operations, only needs to issue an IO channel IO instruction indicating channel program which it is to be executed and the memory address to be accessed IO devices, the channel receives the instruction by executing the channel program will be able to complete the task specified by the CPU IO, visible when the channel is just at the start I / O operations and end issuing I / O interrupt request to the CPU , relative to the previous control mode to further reduce the level of CPU intervention.

cpu frequency interference

Except the starting channel in the I / O operations and sent to the CPU at the end of I / O interrupt request , with respect to the previous control method further reduces the level of intervention of the CPU.

Data transfer unit

Piece

Three, IO core subsystems

Core IO subsystem is mainly to do is IO scheduling, equipment protection, equipment distribution and recovery, buffer management (buffer and cache)

3.1 Buffer Management

If a character device, each finished output a character and finding the CPU issues an interrupt signal

After using the buffer, IO device sends character data to the buffer until the buffer is sent to the CPU in full

Buffer role:

• Ease speed between the CPU and IO device does not match the contradictions
• Reduce the frequency of interrupt to the CPU, easing restrictions on CPU interrupt response time of
• Solve the problem of data size mismatch
• Improving parallelism between the CPU and the IO device

Single buffer

The operating system assigned a buffer in main memory, when the data buffer is not empty, you can not go into the data buffer, the buffer data came only from

Double buffering

The operating system assigns both in main memory buffers

Single / double buffering difference of communication

Communication between the two machines, the buffer may be configured for data transmission and reception

Unidirectional transmission any time, provided a single buffered data can only achieve two machines

If two-way communication can be achieved if the buffer data

Circular buffer

Many of equal size linked into a circular queue buffer

Buffer pool