This tutorial uses the FMQL7045 FPGA development board to complete the entire experiment, and the board photos are as follows:
With rich interface resources, the system block diagram is as follows:
This tutorial is used to complete the LED experiment based on Vivado's FMQL45. The goal is to run the PL side of this development board first.
For pure PL design, our FMQL45 and Zynq7045 are fully compatible in pins, so Vivado can be directly used for logic development, and simple logic can also be developed using Procise, but if you want to use IPcore in large quantities, Vivado is recommended.
Here we first introduce the Vivado process.
The experimental Vivado project is "00_led". The main function of this routine is to control the 8 LED lights on the expansion board to flip once every second.
1 LED hardware introduction
The PL side can only directly control the LED lights on the PL side, and cannot directly control the peripherals on the PS side. The 8 LED lights are connected to the 3.3V power supply through the triode, and the LED will light up when the triode is turned on. Combined with the schematic diagram of the core board and the expansion board, we can see that the pins of the 8 LEDs corresponding to the FMQL45 chip are as follows:
LED1 --- AJ24
LED2 --- AK18
LED3---AB29
LED4---AC27
LED5 --- AD23
LED6 --- AF24
LED7---AE23
LED8---AG25
2 Vivado project establishment
(1) In Windows, you can double-click the Vivado shortcut to start Vivado.
(2) Click "Create Project" in the Vivado development environment to create a new project.
(3) A wizard to create a new project pops up, click "Next"
(4) Enter the project name and project storage path in the pop-up dialog box, we name it 00_led here. It should be noted that there should be no Chinese spaces in the project path "Project location", and the path name should not be too long. Then click Next.
(5) Select "RTL Project" in the project type.
(6) Target language select "Verilog".
(7) Click "Next", do not add any files, and add them later.
(8) Filter out the xc7z045ffg900-2 device and select it, and click "Next".
(9) Click "Finish" to complete the creation of the "led" project.
(10) The figure below is the software interface of Vivado.
3 Create Verilog HDL file
(1) Click the Add Sources icon under the Project Manager, choose to add or create design source files "Add or create design sources", and then click "Next".
(2) Select to create a file "Create File"
(3) In the pop-up window, set the "File name" to "led" and click "OK".
(4) Click "Finish" to complete the addition of the "led.v" file.
(5) At this time, you can specify the "Module name" on the pop-up window, here we just follow the default, click "OK".
(6) Select "Yes" in the pop-up dialog box.
(7) Double-click "led.v" to edit the file.
(8) Write a piece of "led.v" logic code, where a 32-bit register timer is defined, which is used to count 0~499999999 (1 second) in a loop. When the count reaches 499999999, the timer changes to 0 and flips 8 LEDs lamp. On the hardware, the LED will switch on and off every second. Remember to save the code after writing, the source code is as follows:
4 Add pin constraints
The constraint file we use on Vivado is in the XDC format, which mainly completes pin constraints, clock constraints, and group constraints. Here it is necessary to assign the input and output ports in the led.v program to the real pins of the FPGA.
(1) Click "Open Elaborated Design", and click "OK" on the pop-up window.
(2) Select "Window --> I/O Ports" in the menu
(3) You can see the pin assignment in the pop-up I/O Ports.
(4) Give LED and clock frequency division pins and level standards, and save after completion. Please refer to the schematic diagram for the allocation of this block.
(5) A pop-up window asks to save the constraint file. We fill in "led" for the file name, and "XDC" for the file type by default. Click "OK".
(6) Open the newly generated "led.xdc" and you can see the relevant TCL scripts. In fact, we can write them directly after we are familiar with the relevant syntax, instead of generating them through the above graphical interface. Developers are required to familiarize themselves with and learn the relevant syntax, so I won’t go into details here.
In addition to pin constraints, an FPGA design also has timing constraints. Here, a wizard is used to demonstrate how to perform timing constraints.
(1) Click "Run Synthesis" to start the synthesis process.
(2) Click "OK" in the pop-up dialog box.
(3) Click "Cancel" after the synthesis is completed.
(4) Click "Constrain Wizard"
(5) Click "Next" in the pop-up window
(6) Set the "sys_clk" frequency to 50MHz, then click "Skip to Finish" to end the timing constraint wizard.
(7) Click "Finish"
(8) The led.xdc is updated at this time, click "Reload" to reload the file. You can see that the clock constraint is added to the last line.
6 Generate BIT bit stream
(1) The compilation process can be divided into synthesis, layout and routing, bit stream generation, etc. Here we can directly click "Generate Bitstream" to generate bit stream directly with one click.
(2) Select the number of tasks in the pop-up dialog box, which is related to the number of CPU cores. Generally, the larger the number is, the faster the compilation will be, but the more system resources will be occupied. Here the user needs to measure by himself, here we follow the default and click "OK" directly.
(3) Start compiling, and there is compiling status information in the upper right corner of the software.
(4) If there is no error in compiling, a dialog box will pop up for us to choose the follow-up operation. Here we select "Open Hardware Manger" and click "OK" to download and debug.
7 Download and debug
(1) Connect the Jtag interface of the development board, and power up the development board. Click "Auto Connect" on the "HARDWARE MANAGER" interface to automatically scan and connect to the device.
(2) You can see the ARM and FPGA cores scanned by Jtag, and there is also an XADC that can detect system voltage and temperature.
(3) Select xc7z045_1, right click "Program Device..."
(4) Select a specific bit stream path in the pop-up window, and then click "Program".
(5) After the download is successful, we can see that the 8 LED lights change once per second, and the pure PL Vivado process is over.
8 summary
The FMQL45 of domestic Fudan Microelectronics is used to complete the lighting of LED lights, which is also the first step to start the use of domestic FPGA. Further tutorials will be introduced later.
If you are interested in this board, you can refer to the link below for a detailed introduction, domestic FPGA solutions, we are professional!