Disclaimer: The author is engaged in embedded software development, not a professional hardware designer. The content of the notes is output based on his own experience and understanding of the protocol. There must be some places where understanding and translation are not in place. If you have any questions, please refer to the original specification.
PHY is a source synchronous interface (source synchronous interface) in Forward Direction. Whether in Forward or Reverse signal mode, there can only be one clock source. In Reverve Direction, the clock is sent in Forward Direction.
图1 Conceptual D-PHY Data and Clock Timing Reference Measurement Planes
High-Speed Clock Timing
The master side of the link sends a differential clock signal to the slave side for data sampling. This signal is a DDR (half-rate) clock, and the clock signal has one transition per data bit time. All timing relationships for correct data sampling are defined relative to clock transitions. Therefore, in the implementation scheme, the clock may use frequency spreading modulation (frequency spreading modulation) to reduce EMI.
The DDR clock signal maintains a quadrature phase relationship with the data signal. Data is sampled on the rising edge and falling edge of the clock signal. The "rising edge" here refers to the "rising edge" of the differential signal, that is, CLKp - CLKn ("- "represents a minus sign), and the meaning of the "falling edge" is similar. Therefore, the period of the clock signal is the sum of two consecutive instantaneous data bit times (sum of two successive instantaneous data bit times).
图2 DDR Clock Definition
As can be seen from Figure 1, the clock source that generates the DDR clock and initiates the serial data is the same. Since the clock and data signals are co-propagated on a specific skew (skew) channel, the clock in the receiver can be directly used to sample the data signal line. For ongoing bursts, the system is able to adapt to transient changes in the UI defined by . As a forward clock link, it is expected to track with maximum low frequency jitter
. for example:
- 225MHz at 4.5 Gbps
- 125MHz at 2.5Gbps
- 75MHz at 1.5Gbps
The excess dither can be ignored.
For information on clock jitter and skew, you can refer to this article:
https://www.cnblogs.com/amxiang/p/14958329.html 
https://www.cnblogs.com/amxiang/p/14958329.html Allowed instantaneous UI changes can lead to large, instantaneous data rates Variety. Therefore, the device should be equipped with appropriate logic functions to adapt to these transient changes. Some recommended methods, such as taking an appropriate FIFO logic in addition to the PHY, or providing an accurate clock source to the Lane module to eliminate these transient changes, or designing a data sink outside the PHY (data sink outside the PHY) to tolerate UI changes.
The device must meet the Period Jitter limit.
When SSC (Spread Spectrum Clocking) is disabled, Period Jitter is defined as the peak-to-peak deviation of a clock cycle (peak-to-peak deviation) compared to the average value of 32k consecutive clock cycles (not quite understood here, the original text is "the average of 32 k periods of continuous clock cycles").
When SSC is enabled, Period Jitter is defined as the peak-to-peak deviation of a clock period compared to the average clock period of the last one or more complete SSC modulation periods.
图3 Clock Signal Specification