Disclaimer: The author is engaged in embedded software development, not a professional hardware designer. The content of the notes is output based on his own experience and understanding of the protocol. There must be some places where understanding and translation are not in place. If you have any questions, please refer to the original specification.

initialization

All PHYs support LP mode. If the ALP mode is also supported, whether the link uses the LP initialization process or the ALP initialization process is determined by the system implementer.

LP Initialization

After power-on, the Slave side PHY should be $T_{INIT}$ initialized when the Master PHY drives a Stop state (LP-11) and maintains it for more than time. The first $T_{INIT}$ Stop state that exceeds this specified time is called the initialization period (Initialization period). The Master PHY itself is initialized through a system or protocol layer input signal (PPI). The Master side must ensure that before the Master is initialized, there will not be an excessive $T_{INIT}$ Stop state on the signal line. The slave side ignores all signal line states for an unspecified length of time before the initialization cycle.

It should be noted $T_{INIT}$ that is a parameter that depends on the protocol layer, so the specific requirements of $T_{INIT,MASTER}$ and $T_{INIT,SLAVE}$ are defined in the protocol layer specification. However, the D-PHY specification requires the minimum length of the sum, which is not less than 100us in the specification $T_{INIT,MASTER}$ . $T_{INIT,SLAVE}$ A protocol layer specification using the D-PHY specification can specify any value greater than this value, for example $T_{INIT,MASTER} \geq 1 ms$ , $T_{INIT,SLAVE}$ between 500 and 800us.

图1 LP Initialization States

ALP Initialization

After power-on, the Slave side PHY should be $T_{INIT}$ initialized when the Master PHY sends an ALP Wake pulse and maintains it for more than time. Sending this pulse followed by a sequence of transitions to the ALP Stop state is called the Initialization period. The link is to be configured so that the Slave PHY is powered on and ready before the Master PHY sends the initialization sequence. The Master PHY itself is initialized by a system or protocol layer input signal (PPI). $T_{INIT}$ The Master PHY must ensure that the ALP-01 Lane state that the period exceeds the Lane does not appear before initialization . The slave side ignores all signal line states for an unspecified length of time before the initialization cycle.

When the Slave PHY enters the Init state before the Master PHY, Dp and Dn are not driven by the Master PHY. The Slave PHY keeps its differential termination $Z_{ID}$ enabled until an ALP Wake pulse is observed, in order to avoid uncontrolled voltage effects at its receiver input pins, which could cause lead to false triggering of ALP-ED detection. When the Master PHY is powered up, its transmitter may temporarily generate a differential voltage glitch on the line. This voltage spike should be limited below the ALP-ED threshold $V_{IDTL\_ALP}$ to avoid false ALP-ED detection triggers. The Master PHY cannot use the Half Swing mode in the Init state.

图2 ALP Initialization States

图3 Example of Initialization Period after Power-Up

MIPI D-PHYv2.5 notes (14) -- Initialization

initialization

LP Initialization

ALP Initialization

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