1. Digital Logic
first question:
The bit width of input A is 12bit, the bit width of input B is 8bit, and the bit width of input C is 4bit. To realize Y=A*B+C, it is required that the algorithm of this module does not lose precision, and the minimum bit width of Y is defined as appropriate ( )
A. 20
B. 21
C. 16
D. 24
(A)
A is 12bit, B is 8bit, A*B is 20bit. If a 20bit data plus a 4bit data needs a 21bit wide variable to store. But the maximum value of A*B+C is 12'hFFF * 8'hFFF + 4'hF = 20'hFEF10. So A*B+C needs 20bit.
Second question:
The binary expression corresponding to decimal 46.25 is ( )
A. 101110.11
B. 101101.01
C. 101110.1
D. 101110.01
(D)
Integer part: 101110, decimal part: 0b0.01 = 1/2^2=0.25, so the decimal part is 01. It is also possible to obtain the representation of the fractional part according to the traditional method of continuously multiplying by 2. So the result is 101110.01
The third question:
In the state transition table of the sequential circuit, if the state number N=3, when the one-hot code is used for encoding, the state variable bit width is at least ( )
A. 4
B. 8
C. 2
D. 3
(D)
The state transition of sequential circuits is mainly about the state machine. There are three main ways to encode state variables, one-hot code, binary code and Gray code. If one-hot code is used, the number of 3 states is 3'b001, 3'b010, 3'b100, 3 digits are required. If binary code is used, the 3-state numbers are 2'b00, 2'b01, 2'b10, requiring two bits. If Gray code is used, the 3-state numbers are 2'b00, 2'b01, 2'b11, requiring two bits. So the result is 3 bits.
Fourth question:
Which of the following is not a method for describing the function of a combinational logic circuit ( )
A. Truth table
B. Boolean equation
C. State machine
D. Logic block diagram
(C)
Truth tables and Boolean equations are the most basic ways to describe circuit functions. Logic block diagrams are similar to gate-level circuits. Circuits are drawn directly through logic diagram symbols, which are common in RTL. The state machine is a sequential circuit, and the state machine is generally described by a state transition diagram.
Fifth question:
The general characteristics of sequential logic circuits do not include ( )
A. The state of the system is maintained or changed depending on the input to the system and its current state
B. The state diagram and state table of a sequential machine are two different representations of the same design information
C. There can be no clock
D. The current state and input signal of a sequential circuit (machine) determine its next state and output
(C)
The remaining three are the characteristics of sequential logic circuits, and sequential logic circuits cannot be without clocks.
Sixth question:
There are ( ) ways to eliminate competition hazards in combinational logic circuits
A. Connect the filter capacitor at the output
B. Post-stage plus buffer circuit
C. Shield the spike interference of the input signal
D. Pre-amplification resistance
(A)
Usually, the way to eliminate the risk of competition in combinational logic is to connect filter capacitors to the input. Adding a buffer to the power stage does not filter out race-hazard glitches. Due to the delay effect of the logic gate, the competition hazard phenomenon is mainly caused by the simultaneous transition of two input signals to the opposite logic level, rather than by the spike interference of the input signal, so the spike interference of the input signal is shielded Adding resistance to the previous stage cannot eliminate the burr output after the combinational logic.
Seventh question:
How is the Tsu (establishment time) of the register defined ( )
A. The time the data remains stable after the clock edge
B. The time before and after the clock edge brings the data to be stable
C. Time for data to remain stable throughout a clock cycle
D. The time the data remains stable before the clock edge arrives
(D)
The basic concept of Tsetup, the time that the data remains stable before the clock edge arrives.
Eighth question:
Combinational logic circuits are ( )
A. Full adder
B. Shift register
C. Counter
D. Trigger
(A)
Full adder (common sense), if you don't understand, look at the circuit diagram.
Ninth question:
Among the following logic circuits, which is not a combinational logic circuit is ( )
A. Encoder
B. Triggers
C. Adder
D. Decoder
(B)
Flip-flop (common sense), if you don’t understand, look at the circuit diagram
Tenth question:
Signals A and B are both 4bit input, C = A+B, signal C should define ( ) bit
A. 4
B. 5
C. 6
D. 3
(B)
Both inputs are 4bit, in order not to overflow the data, it is enough to define 5bit. An example of adding the maximum values is 4'hF + 4'hF = 5'h1E. Note the difference from the first question.