(1) Without affecting the logic function, the redundant input terminal of the CMOS NAND gate can be _____.
A. Connected to high level
B. Connected to low level
C. Floating
D. Grounded through a resistor
Parse:
-
CMOS NAND gate : As long as one input is low level, it will be low level after the AND operation, and the negative output will be high level, which will affect the result. If it is grounded or suspended, the output will always be 1.
-
CMOS AND gate, NAND gate : the redundant input terminal is connected to the power supply through a current limiting resistor (500Ω), that is, connected to a high level;
-
CMOS OR gate, NOR gate : the redundant input terminal is grounded through the current limiting resistor, that is, connected to low level;
-
TTL AND gate, NAND gate :
a: Connect the redundant input terminal to high level, that is, connect it to the power supply through a current limiting resistor;
b: Connect to the ground through a large resistor (greater than 1K), which is equivalent to connecting the input terminal to high level;
c: Leave the redundant input terminal floating (equivalent to Because there is a large resistance), it is equivalent to the input terminal connected to a high level; -
TTL OR gate, NOR gate : connected to the ground through a resistance less than 1KΩ.
Answer: A
(2) To generate sequence signal 11010111, at least _____ level trigger is required.
A.2
B.3
C.4
D.5
Parse:
- Sequence length N=8, 2^3=8, at least 3 levels of flip-flops; if a shift register is used, at least 5 levels of flip-flops are required
Answer: D
(3) An 8-bit binary subtraction counter, the initial state is 00000000, after 268 input pulses, the state of this counter is _____.
A.11001111
B.11110100
C.11110010
D.11110011
Parse:
- 2^8=256, count 256 times and return to 0000_0000, 268-256=12, after counting 1 time, 0000_0000 - 0000_0001 = 1111_1111, after counting 11 times, 1111_1111 – 0000_1011 = 1111_0100
Answer: B
(4) The shift register is composed of 8-stage flip-flops, and the twisted ring counter formed by it has _____ effective states; the ring counter formed by it has _____ effective states, and the linear feedback shift register has _ ____ valid states.
A.16，8，511
B.4，8，15
C.16，8，255
D.8，16，127
Parse:
- Twisted ring counter: only one flip-flop flips every time it changes, there is no risk of competition in decoding, and 2n states are used;
- Ring counter: only one of all flip-flops is in 1 state, and counting N times requires N flip-flops;
- Linear Feedback Shift Register: 2^n – 1.
Answer: C
(5) If an XNOR gate is to be used as an inverter (NOT gate), the connection method of the input terminals A and B is ______.
One of AA or B is connected to "1"
BA or one of B is connected to "0"
CA and B are used in parallel to use
D. Cannot be realized
Parse:
- XOR: XOR with 0 or itself. After negation is the negation of the input, which is equivalent to an inverter.
Answer: B
(6) The Mealy-type synchronous sequential circuit to achieve the same function requires _____ more than the Moore-type synchronous sequential circuit.
A. More states
B. Fewer states
C. More triggers
D. Fewer triggers
Parse:
- Mealy: the output is related to the current state and the input;
- Moore: the output is related to the current state;
- Mealy is one clock cycle ahead of Moore (one shot); the number of Moore states is one more.
Answer: B
(7) Assuming that the value of a variable a with a 4-bit width is 4'b1011, calculate the result of the following operation expression: &a, {3{a}}, ~a, {a[2:0], a[3 ]}, (a<4'd3) || (a>=a), !a
Parse:
- &: bitwise and;
- &a: The bits in a are ANDed, the result is 1bit, there is 0 in a, and all bits are ANDed to output 1'b0;
- &&: Logical AND;
- ~: bitwise inversion;
- ! : logical negation;
(8) The initial values of the signals in, q1, q2 and q3 in the following two codes are 0, 1, 2 and 3 respectively, then after one clock cycle, the value of q3 in the program on the left becomes (), and the value of q3 in the program on the right The value of q3 in the side program becomes ().
Parse:
- Blocking assignment =: blocking refers to waiting until the end of the current assignment statement before assigning the next statement, that is, in assigns q1, q1 assigns q2, and q2 assigns q3;
- Non-blocking assignment <=: There is no influence between different assignment statements, and the value 2 of q2 in the previous clock cycle is assigned to q3 at the next clock edge.
Answer: 0, 2
(9) The total delay of a large combined circuit is 100ns, and the assembly line is used to divide it into two smaller combined circuits. Theoretically, the highest operating frequency of the circuit can reach ().
Parse:
- Split each delay is 50ns, that is 20MHz.
Answer: 20MHz
(10) There are two types of block statements, one is the begin-end statement, which is usually used to mark () the execution of the statement; the other is the fork-join statement, which is usually used to mark the () execution of the statement.
Parse:
- begin-end: statements are executed one by one in order; fork-join: parallel block, the statements in the block are executed at the same time.
Answer: sequential, parallel
(11) In high-speed system design, which of the following optimization schemes is not aimed at increasing the operating frequency of the system ().
A. Pipeline
B. Tree structure
C. Delayed signal shifting
D. Resource sharing
Parse:
- Area optimization, improve resource utilization to reduce power consumption: serialization, resource sharing, logic optimization;
- Speed optimization to improve running speed: pipeline design, register trimming, critical path optimization, delayed signal shifting.
Answer: D
(12) The coding style of the state machine includes one-stage, two-stage and three-stage. The following description is correct ()
A. One-stage register output is prone to glitches, which is not conducive to timing constraints;
B. Two-stage combinational logic output does not generate glitches, which is conducive to timing constraints;
C. Three-stage register output does not generate glitches, which is conducive to timing constraints ;
D. All description styles are register output, which is prone to glitches and is conducive to timing constraints.
Parse:
-
The two-stage sequential logic is separated from the combinational logic, and the current state is output by the combinational logic, which may cause glitches due to competition risks, and is not conducive to constraints.
-
Both one-stage and three-stage are register outputs.
-
The three-stage method is compared with the two-stage method: the register output is realized without inserting additional clock beats.
Answer: C
(13) Regarding the process block and process assignment description, the following is correct ()
A. The signal on the left side of the expression in the procedural assignment statement must be a register type;
B. The statement in the procedural block must be synthesizable;
C. In the procedural block, using the procedural assignment statement to assign a value to wire will not cause an error;
D , The types of timing control in the process block are simple delay, edge sensitive and level sensitive.
Parse:
- Process assignment: There are two types of process assignment blocks: initial block and always block. Both statements are executed in parallel, and if combined with begin-end, they are executed sequentially. The assigned data type must be a register type variable (reg);
- Continuous assignment: used in combinational logic, any change in an input immediately updates the output. The assigned data type must be a wire type variable, such as assign out=a;
Answer: A
(14) Which of the following statements about the description of the function is incorrect ()
A. The function definition cannot contain any timing control statement;
B. The function has at least one input, including any output or bidirectional port;
C. The function only returns one data, which defaults to the reg type;
D. The function cannot call tasks, but Tasks can call functions.
Parse:
- A: The function definition cannot contain any control statements (#, @, wait), delay, time and timing control structures can be used in the task;
- B: The function has at least one input, and cannot contain any output and bidirectional ports. Tasks can have multiple input, bidirectional and output variables;
- C: The function has a return value. By default, it returns 1'bit register reg data by default, and the task task has no return value;
- D: Functions cannot start tasks, and tasks can start other tasks or functions.
Answer: B