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1. Purpose of the experiment
(1) Learn the basic operations of Quartus Prime, Platform Designer, and Nios II SBT;
(2) Get a preliminary understanding of the SOPC development process, and basically master the Nios II soft core customization method;
(3) Master the Nios II software development process, software Basic tuning method.
2. Experimental equipment
Hardware: PC, DE2-115 FPGA experimental development platform;
Software: Quartus Prime 18.1, Platform Designer, Nios II SBT
3. Experimental content
Use FPGA resources to build a simple Nios II processor system, including:
(1) Create a project in Quartus Prime;
(2) Use PD to build and generate a simple Nios II-based hardware system;
(3) Build a project in Quartus Prime Compile the hardware system based on Nios II in the project and generate the configuration file .sof;
(4) Create a user C/C++ project corresponding to the hardware system in Nios II SBT, write a simple user program, and compile the program in
Nios II SBT to generate a Execution file .elf;
(5) Download configuration file .sof and executable file .elf to FPGA for debugging and running.
4. Experimental principle
The user program code for controlling the flashing of the LED light is very small and can be solidified in the on-chip ROM for execution. Variables, stacks
and other spaces use on-chip RAM and do not use any off-chip memory.
5. Experimental steps
1. Create a project
Select the chip, EP4CE11529C7 of Cyclone IV E series.
2. Qsys system design
Click platform designer
to change the name to kernel, click save,
right click clk_0, select edit, and set 50M.
Add peripheral devices:
search for Nios II Processor, click add,
rename nios2_qsys_0 to cpu,
connect clk and reste_n of cpu to clk and clk_reset of system clock clk_0 respectively,
add jtag uart interface,
search for JTAG UART, click add, and keep the default settings.
jtag-uart_0 renamed to jtag-uart.
Add RAM core
Search for On Chip, click Add, set memory to 40960
Add PIO interface
Search for pio, click Add, Width is 8bits, Direction selects output, and other options remain default.
Rename it to pio_led, double-click on the Export column to lead out the output port, and name it out_led.
Add slice System ID Peripheral core
Search for System ID Peripheral, click Add, keep the default setting.
Renamed to sysid.
The general diagram of the port connection is as follows:
Add base address:
specify the reset and exception address of NIos II: select the CPU, right-click, and click edit to enter Nios II
On the configuration interface of Processor, configure Reset Vector and Exception Vector as
"onchip_ram.s1":
Click "Create Global Reset Network" under "System" in the menu bar of the Qsys main interface. All reset ports are automatically connected after completion.
Generate Qsy system
3. Logical connection
Add our generated Qsy file in the schematic file.
Click the menu Project-add/remove files in project, click the browse button on the right to find the qip file as shown in the figure, select it and click add to add it.
Select Assignments-device in the menu, then click Device and Pin Options, and set the unused pins to As input tri-stated
Bind pins:
to compile.
4. Software design
Click Tools, then Nios II Software Build Tools for Eclipse to open Nios II SBT for Eclipse.
Create a project:
select and set as shown in the figure below.
code:
#include "stdio.h"
#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "alt_types.h"
const alt_u8
led_data[8]={
0x01,0x03,0x07,0x0F,0x1F,0x3F,0x7F,0xFF};
int main (void) {
int count=0;
alt_u8 led;
volatile int i;
while(1)
{
printf("Hello world!\n");
if(count == 7)
{
count = 0;
}
else
{
count++;
}
led=led_data[count];
IOWR_ALTERA_AVALON_PIO_DATA(PIO_LED_BASE, led);
i = 0;
while (i<500000)
i++;
}
return 0;
}
Right-click bsp, select Nios II, Generate BSP
right-click the project, build project
5. Burning
Click the button on the software toolbar, and the download interface will appear. The first download requires hardware installation. That is, click the button "hardware setup..." in the download interface, then select "USBblaster" in the pop-up dialog box, and then click "ok", then the hardware is installed.
After installing the hardware, add the corresponding download file in output_files.
In the menu bar, select Run →Run Configurations
and click refresh, apply, and run in the figure below.
Running result:
Click the button to reset.
Six, Verilog realizes the water lamp
Here, since the methods of project establishment and setting are similar, only the code is given as follows:
module waterlight (
input wire clk ,
input wire rst_n ,
output [7:0] led
);
parameter CNT_MAX = 26'd5000_0000;
reg [25:0] cnt_1s;//1s 计数器，计数最大值 5000_0000 - 1
wire flag_1s;//计数器每计满1s，使能一个时钟周期
reg [7:0] led_reg;//输出信号的寄存信号
//1s计数器
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
cnt_1s <= 26'd0;
else if(cnt_1s >= CNT_MAX - 26'd1) //归零条件
cnt_1s <= 26'd0;
else
cnt_1s <= cnt_1s + 26'd1;
end
assign flag_1s = cnt_1s >= CNT_MAX - 26'd1;
//移位实现流水灯
always@(posedge clk or negedge rst_n)begin
if(!rst_n)
led_reg <= 8'b1111_1111;//全灭
else if(flag_1s)
if(led_reg == 8'b1111_1111)
led_reg <= 8'b0000_0001;
else
led_reg <= {
led_reg[6:0],led_reg[7]};//拼接实现循环移位
else
led_reg <= led_reg;
end
assign led = led_reg;
endmodule
The burning operation result here is the same as last time.
7. Summary
This experiment is mainly to understand and be familiar with the operation method of Nios-II soft core, configure the Qsy file by yourself, mainly to familiarize and practice the operation, and also have some knowledge about the use of Eclipse and how to connect it to the FPGA development board. Got some understanding.
8. References
Realization of water lamp based on NIOS-II soft core and verilog language