It mainly introduces the usage of assembly instructions.
1. LDR
instruction description: read memory instruction
Example 1: LDR R0, [R1]
example description: Assume the value of address R1 is x, read the data (4 bytes) at address x and save it to R0.
Example 2: LDR R0, 0X0209C004
Example description: Assign the value at the address of 0X0209C004 to R0
2. LDR (pseudo-instruction)
instructions: pseudo-instructions (instructions that do not exist, and are finally parsed into real assembly instructions)
Example: LDR R0,=0x12345678
Example explanation: assign the value of 0x12345678 to R0.
3. STR
instruction description: write memory instruction
Example 1: STR R0,[R1]
example description: Assuming the value of R1 is x, write R0 data to address R1.
Example 2: STR R0, [R1, #8]
example description: write the word data in R0 into the memory whose address is R1+8.
Example 3: STR R0, [R1], #8
Example description: Write the word data in R0 into the memory with R1 as the address, and write the new address R1+8 into R1
4.
Explanation of MOV instruction: Assignment instruction
Example 1: MOV R0, R1
Example explanation: Assign the value of R1 to R0, that is, R0=R1.
Example 2: MOV R0, #0x100
Example description: assign 0x100 to R0 //#0x100 is expressed as an immediate value
5. LEA
instruction description: take effective address instruction
Example 1: LEA REC, OPRD
Example description: transfer the effective address of the operand oprd to the operand rec, the source operand oprd must be a memory operand, and the destination operand rec must be A 16-bit or 32-bit general-purpose register.
Note: The difference with the mov instruction: mov: move the value in the address; lea: move the address.
6.
Explanation of JMP instruction: direct transfer instruction in the unconditional segment
Example 1: JMP LABEL
example explanation: make the control unconditionally transfer to the position labeled label. The unconditional branch instruction itself does not affect the flag
7. CALL
instruction description: procedure call instruction
Example 1: CALL LABEL
Example description: call LABEL directly in the segment
Note: The difference from jmp is that the call instruction will save the return address before calling the label (the main program can continue to execute after the return in call , jmp cannot return to the main program to continue execution after the label execution is completed)
8.
Description of command B: jump command. //Used for the process of jumping out of the function and not coming back
Example:
_start
ldr sp, =0x80200000 //sp is the pointer to the top of the stack, here is to set the stack pointer
b main
Example description: jump to the main function
9. BL
instruction description: jump instruction. //It is used to return to continue the process of the current function after the function call.
Example:
Example description:
Note: Compared with the B instruction, the BL instruction will save the current PC register value in the register LR (R14) before jumping, so you can pass The value in the LR register is reloaded into the PC to continue execution from where the code was before the jump.
10.
Explanation of SAL instruction: Arithmetic left shift
Example 1: SAL OPRD, count
Example explanation: Shift the operand oprd to the left by count bits, and add 0 to the right.
11.
Explanation of SHL instruction: Logical left shift
Example 1: SHL OPRD, count
Example explanation: Shift the operand oprd to the left by count bits, and add 0 to the right.
Note: Same as shl command. By truncating the lower 5 bits of count, the actual number of shifts is limited to between 0 and 31.
12. SAR
instruction description: Arithmetic shift right
Example 1: SAR OPRD, count
Example description: Shift the operand oprd to the right by count bits, and at the same time shift one bit to the right, complement the sign bit on the left, and the lowest bit shifted out enters the flag bit CF.
13.
Explanation of SHR instruction: Logical right shift
Example 1: SHR OPRD, count
Example explanation: Shift the operand oprd to the right by count bits, add 0 to the left, and the lowest bit shifted out enters the flag bit CF.
14.
Explanation of ROL instruction: Left circular shift instruction
Example 1: ROL OPRD, count
Example explanation: Shift the operand oprd to the left by count bits.
15. ROR
instruction description: right circular shift instruction
Example 1: ROR OPRD, count
example description: shift the operand oprd to the right by count bits.
16.
Explanation of RCL instruction: Left circular shift with carry
Example 1: RCL OPRD, count
Example explanation:
17.
Explanation of RCR instruction: right cyclic shift with carry
Example 1: RCR OPRD, count
Example explanation:
18. LOOP
instruction description: counting loop instruction
Example 1: LOOP LABEL
example description:
19. SUB
instruction description: Subtraction instruction
Example 1: sub r0,r1,#5
Example description: r0 = r1 - 5.
Example 2: sub r0,r1,r2
Example explanation: r0 = r1 - r2.
20.
Explanation of SBC instruction: subtraction with borrow
Example: SBC Rd, Rn, #immed
Example explanation: Rd = Rn - #immed - borrow.
Example 2: SBC Rd, Rn, Rm
Example explanation: Rd = Rn - Rm - Borrow.
21.
Description of ADD instruction: Addition instruction
Example: add r0, r1, #5
Example explanation: r0 = r1+5.
Example 2: add r0,r1,r2
example description: r0 = r1 + r2
22. ADC
instruction description: addition operation with carry
Example: adc Rd, Rn, Rm
Example description: Rd = Rn + Rm + carry
Example 2: add Rd, Rn, #immed
Example description: Rd = Rn + #immed + carry
23. MUL
instruction description: Multiplication instruction
Example: MUL Rd, Rn, Rm
Example description: Rd = Rn * Rm
24. UDIV
instruction description: unsigned division instruction
Example: UDIV Rd, Rn, Rm
Example description: Rd = Rn / Rm
25. SDIV
instruction description: signed division instruction
Example: UDIV Rd, Rn, Rm
Example description: Rd = Rn / Rm
26. CMP
instruction description: Compare the size of two operands
Example: cmp oprd1, oprd2
Example description: Perform the implicit subtraction operation of subtracting the source operand from the destination operand, and do not modify any operands.
Note: It affects the CF, ZF, OF, AF, and PF of the flag. The description is as follows:
If the instruction is executed: ZF=1, it means that the two numbers are equal, because zero is 1 and the result is 0.
When there is no sign:
if CF=1, it means that there is a carry or borrow, cmp is a subtraction operation, so it can be seen as a borrow, so at this time oprd1<oprd2; CF=0, it means that there is no borrow, but at this
time Pay attention to whether ZF is 0, if it is 0, it means that the result is not 0, so at this time oprd1>oprd2. When
signed:
if SF=0, OF=0, it means that the value at this time is positive and there is no overflow , it can be seen intuitively that oprd1>oprd2;
if SF=1, OF=0, it means that the value at this time is negative, and there is no overflow, then it is oprd1<oprd2;
if SF=0, OF=1, it means that When the value is positive and there is overflow, it can be seen that oprd1<oprd2;
if SF=1, OF=1, it means that the value at this time is negative and there is overflow, it can be seen that oprd1>oprd2;
27.
Description of the TEST instruction: The instruction performs an AND operation between the corresponding bits of the two operands, and sets the sign flag, zero flag, and parity flag according to the operation result Example:
test
eax, 100b ; the b suffix means binary
jnz ***** ; If the third bit from the right of eax is 1, jnz will jump
Example: The condition of jnz jump is not 0, that is, ZF=0, ZF=0 means that the zero flag is not set , that is, the logical AND result is 1.
Example 2:
test ecx, ecx
jz somewhere
If ecx is zero, set the ZF zero flag to 1, and Jz jumps
Note: TEST AX, BX has the same effect as AND AX, BX command, but the Test command does not change the contents of AX and BX , and the AND instruction will save the result to AX
Note: Condition code description:
Condition code:
OF (Overflow Flag) overflow flag, when overflow is 1, otherwise it is set to 0. It indicates an overflow calculation, such as: the structure and the target are not match.
SF (Sign Flag) sign flag, set to 1 when the result is negative, otherwise set to 0.
ZF (Zero Flag) Zero flag, set to 1 when the operation result is 0, otherwise set to 0.
CF (Carry Flag) Carry flag, set to 1 when carrying, otherwise set to 0. Note: The Carry flag stores the rightmost bit after calculation.
AF (Auxiliary carry Flag) Auxiliary carry flag, recording the carry position generated by the third bit (half byte) during operation.
1 when there is a carry, otherwise set to 0.
PF (Parity Flag) parity flag. Set to 1 when the number of 1 in the result operand is even, otherwise set to 0.
Control flag:
DF (Direction Flag) direction flag, which controls the direction of information in string processing instructions.
IF (Interrupt Flag) interrupt flag.
TF (Trap Flag) trap flag.
28.
Explanation of BNE instruction: it is a conditional jump, that is, it is "not equal (or not 0) jump instruction". If it is not 0, jump to the address specified later and continue to execute.
Example:
TST R0, #0X8
BNE SuspendUp; BNE instruction is "not equal (or not 0) jump instruction":
LDR R1, #0x00000000
Example description: Perform the AND operation first, if the fourth bit of R0 is not 1, the result is zero, then set zero=1 (continue to the following LDR instruction). Otherwise, if the fourth bit of R0 is 1, zero=0 (jump to SuspendUp to execute).
29. BEQ
instruction description: it is a conditional jump, that is, it is "jump instruction when it is equal to 0".
Example:
TST R0, #0X8
BEQ SuspendUp; BNE instruction is "not equal (or not 0) jump instruction":
LDR R1, #0x00000000
Example description: first perform the and operation, if the fourth bit of R0 is not 1, If the result is zero, then set zero=1 and execute the BEQ jump. Otherwise, if the fourth bit of R0 is 1, set zero=0 and execute the LDR part.
Note: tst and bne are used together: first use tst to perform bit-AND operation, and then compare the result of bit-AND with 0, if it is not 0, jump to the mark immediately following bne (such as bne sleep, jump to sleep) .
tst and beq are used in conjunction: first use tst to perform a bit-AND operation, and then compare the result of the bit-AND with 0. If it is 0, then jump to the mark immediately following beq (such as bne AAAA, then jump to AAAA)
30. MRS
instruction description: used to transfer the contents of the program status register to the general register.
Format: MRS{Condition} General register, program status register (CPSR or SPSR)
Example 1: MRS R0, CPSR
Example description: Send the content of CPSR to R0.
Example 2: MRS R0, SPSR
example description: send the content of SPSR to R0.
Note:
The MRS instruction is used to transfer the contents of the program status register to the general-purpose register
. Write back the program status register
2) When exception handling or process switching, the value of the program status register needs to be saved, you can use this command to read the value of the program status register first, and then save
31. MSR
instruction description: transfer the content of the operand to a specific field of the program status register. Among them, the operand can be a general-purpose register or an immediate value.
Format: MSR{condition} Program status register (CPSR or SPSR)_<field>, operand
Example 1: MSR CPSR, R0
Example description: transfer the content of R0 to CPSR
Example 2 : MSR SPSR, R0
example description: transfer the content of R0 to SPSR
Example 3: MSR CPSR_c, R0
example description: transfer the content of R0 to SPSR, but only modify the control field in CPSR
Note:
<field> is used to set the program status The bits that need to be operated in the register, the 32-bit program status register can be divided into 4 fields:
1) Bit [31:24] is the condition flag bit field, denoted by f;
2) Bit [23:16] is the status bit field , represented by s;
3) Bit [15:8] is an extended bit field, represented by x;
4) Bit [7:0] is a control bit field, represented by c;
this instruction is usually used to restore or change the program status register When using the content, it is generally necessary to indicate the domain to be operated in the MSR instruction.
32.
Description of the BIC instruction: The BIC instruction is used to clear some bits of (operand 1) and place the result in the destination register. (operand1) shall be a register, (operand2) may be a register, a register to be shifted, or an immediate value. (Operand 2) is a 32-bit mask. If a bit is set in the mask, the returned bit is cleared. Mask bits that are not set remain unchanged.
Format: BIC{condition}{S} Destination register, operand 1, operand 2
Example 1: bic r0, r0, #0x1f
Example description: clear the bit[4:0] of r0.
Example 2: BIC Rd, Rn
Example explanation: Rd = Rd & (~Rn)
Example 3: BIC Rd, Rn, Rm
Example explanation: Rd = Rn & (~Rm)
33. AND
instruction description: bitwise AND
Example 1: AND Rd, Rn
Example description: Rd = Rd & Rn.
Example 2: AND Rd, Rn, #immed
Example explanation: Rd = Rn & #immed
Example 3: AND Rd, Rn, Rm
Example explanation: Rd = Rn & Rm
34.
Description of ORR instruction: bitwise or
Example 1: ORR Rd, Rn
Example description: Rd = Rd | Rn.
Example 2: ORR Rd, Rn, #immed
Example explanation: Rd = Rn | #immed
Example 3: ORR Rd, Rn, Rm
Example explanation: Rd = Rn | Rm
35.
Description of ORN instruction: bitwise OR NOT
Example 1: ORN Rd, Rn
Example description: Rd = Rd |(~ Rn)
36. INC
instruction description: add 1 instruction
Example 1: INC DEST
example description:
37.
Explanation of DEC instruction: Minus 1 instruction
Example 1:
Explanation of DEC DEST example:
38. NEG
instruction description: complement instruction
Example 1: NEG OPRD
example description:
39.
Explanation of EOR instruction: bitwise exclusive OR
Example: EOR Rd, Rn
Example explanation: Rd = Rd ^ Rn.
40. PUSH
instruction description: store the register list in the stack
Format: PUSH
Example 1: PUSH {R0~R3, R12}
example description: push R0~R3 and R12 onto the stack.
Example 2: PUSH {LR}
example description: push LR to the stack
41.
Description of POP instruction: Restore register list from stack
Format: POP
Example 1: POP {LR}
Example description: Restore LR first.
Example 2: POP {R0~R3,R12}
example description: restore R0~R3,R12
42. NOP
instruction description: no operation instruction, used as a delay. It has no effect and occupies one byte of memory space where the instruction is written.
Example: LDR R0, [R1]
Example description: Assuming the value of R1 is x, read the data (4 bytes) at address x and save it to R0 .
43.
Explanation of XCHG instruction: exchange instruction
Example: XCHG OPER1, OPER2
Example explanation: exchange the content of operand oper1 with the content of operand oper2. oper1 and oper2 can be general-purpose registers or storage units, but they cannot be operating units at the same time, nor can they be immediate values.
44. LDM
instruction description: load multiple data, load the value on the address to the register
Format: LDM{cond} mode Rn{!}, reglist{^}
Example:
Ldr R1,=0x10000000 //The starting address of the transmitted data 0x10000000
LDMIB R1!,{R0,R4-R6}
Example explanation: load from left to right, equivalent to LDR R0, 10000004 LDR R4, 10000008...
/*Add +4 to the address before transmission,
so add 4 to the address, R0=0X1000004 The content in the address,
add 4 to the address, R4=0X10000008 the content in the address,
add 4 to the address, R5=0X1000000C the content in the address,
add 4 to the address, R6=0X10000010 the content in the address,
because!, the last address is written back In R1, R1=0X10000010.
45. STM
instruction description: multi-data storage, store the value of the register to the address
Format: STM{cond} mode Rn{!}, reglist{^}
Example: stmia sp, {r0 - r12} //Pay attention to the - here The number is not a subtraction, but a range
example: store r0 in the memory pointed to by sp (assumed to be 0x30001000); then address +4 (that is, point to 0x30001004), and store r1 in this address; then address +4 (point to 0x30001008 ), store r2 into this address until the content of r12 is put into (0x3001030), and the instruction is completed. That is, the content of r0~r12 is stored in the content space with sp as the starting address.
Note:
1) 8 kinds of suffixes, as follows:
ia (increase after) transmits first, then address +4
ib (increase before) transmits address +4 first, then transmits
da (decrease after) transmits first, then address -4
db (decrease before ) first address -4, then transfer
fd (full decrease) full decrement stack
ed (empty decrease) empty decrement stack
fa (·······) full increment stack
ea(·······) empty increment stack
2) ! : Indicates that the last address is written back to Rn
3) reglist: can contain more than one register range, separated by ",", such as {R1, R2, R6-R9}, the registers are arranged in order from small to large
4) ^ : Do not allow running in user mode and system mode