03: CPU cache and memory barrier

CPU cache

        The presence of three levels:

            

Note: No CPU has its own cache L1 and L2, but the multi-core shared L3. 
      CPU reads the data: L1 > L2> L3> memory> hard disk 
data consistency problem more cache: 
    a plurality of cache simultaneously hold a data, who will be modified admit it, CPU manufacturers to discuss an agreement, called MESI protocol. 
    MESI protocol adds four states for the data cache:

            

    Multiprocessor is: CPU data cache to be notified of changes to other cpu. 
Rearrangement CPU operation instruction 
    executed after the CPU will be instruction sequencing. (Does not change the result) since L3 cache is shared. For the purpose of not waiting, CPU execution control sequence of instructions. In order to improve the efficiency of the parallel. 
Memory barriers 
    CPU provides two memory barrier instructions:
             1 : Write memory barrier: Modifications to the cache to be forced to synchronize after the main memory can be used by other CPU.
            2: Read memory barrier: to force cached data synchronization to the main memory.